82091AA Datasheet, PDF (62/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
6 0 PARALLEL PORT
The 82091AA parallel port can be configured for
four parallel port modes These parallel port modes
and the associated parallel interface protocols are
Parallel Port Mode Parallel Interface Protocol
ISA-Compatible Mode
Compatibility Nibble
PS 2-Compatible Mode Byte
EPP Mode
EPP
ECP
ECP
ISA-Compatible PS 2-Compatible and EPP modes
are selected through 82091AA configuration (see
Section 4 0 AIP Configuration) ECP is selected by
programming the ECP Extended Control Register
(ECR)
In ISA-Compatible mode the parallel port exactly
emulates a standard ISA-style parallel port The par-
allel port data bus (PD 7 0 ) is uni-directional The
compatibility protocol transfers data to the peripher-
al device via PD 7 0 (forward direction) Note that
the Nibble protocol permits data transfers from the
peripheral device (reverse direction) by using four
peripheral status signal lines to transfer 4 bits of
data at a time
PS 2-Compatible mode differs from ISA-Compatible
mode by providing bi-directional transfers on
PD 7 0 A bit is added to the PCON Register to al-
low software control of the data transfer direction
For both the ISA-Compatible and PS 2-Compatible
modes the actual data transfer over the parallel port
interface is accomplished by software handshake
(i e automatic hardware handshake is not used)
Software controls data transfer by monitoring hand-
shake signal status from the peripheral device via
the PSTAT Register and controlling handshake sig-
nals to the peripheral device via the PCON Register
EPP mode provides bi-directional transfers on
PD 7 0 The 82091AA automatically generates the
address and data strobes in hardware
ECP is a high performance peripheral interface
mode This mode uses an asynchronous automatic
handshake to transfer data over the parallel port in-
terface In addition the parallel port contains a FIFO
for transferring data in ECP mode The ECP register
set contains an Extended Control Register (ECR)
that provides a wide range of functions including the
ability to operate the parallel port in either ECP ISA-
Compatible or PS 2-Compatible modes
NOTE
In general this document describes parallel
port operations and functions in terms of
how the 82091AA parallel port hardware op-
erates Detailed descriptions of the parallel
interface protocols are beyond the scope of
this document Readers should refer to the
proposed IEEE Standard 1284 for detailed
descriptions of the Compatibility Nibble
Byte EPP and ECP protocols
Special circuitry on the 82091 prevents it from being
powered up or being damaged while a parallel port
peripheral is powered on and the 82091 is powered
off
6 1 Parallel Port Registers
This section is organized into three sub-sections
ISA-Compatible and PS 2-Compatible Modes EPP
Mode and ECP Mode Since the register sets are
similar for ISA-Compatible and PS 2-Compatible
modes (differing by a direction control bit in the
PCON Register) the register set descriptions are
combined The EPP mode and ECP mode register
sets are described separately Each register set de-
scription contains the I O address assignment and a
complete description of the registers and register
bits Note that the PSTAT and PCON Registers are
common to all modes and for completeness are re-
peated in each sub-section Any difference in bit op-
erations for a particular mode is noted in that partic-
ular register description
The registers provide parallel port control status in-
formation and data paths for transferring data be-
tween the parallel port interface and the 8-bit host
interface All registers are accessed as byte quanti-
ties The base address is determined by hardware
configuration at powerup (or a hard reset) or via soft-
ware configuration by programming the 82091AA
configuration registers as described in Section 4 0
AIP Configuration The parallel port can be disabled
or configured for a base address of 378h (all
modes) 278h (all modes) or 3BCh (all modes ex-
cept EPP and ECP) This provides the system de-
signer with the option of using additional parallel
ports on add-in cards that have fixed address de-
coding
62