82091AA Datasheet, PDF (93/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
ISA-Compatible FIFO Mode (ECR 7 5 ^e010)
The ISA-Compatible FIFO mode uses the same sig-
naling protocol on the parallel port interface as the
ISA-Compatible mode However there are two ma-
jor operational differences First data is written to a
16-byte FIFO (via the SDFIFO address location)
The FIFO empty and FIFO full bits in the ECR pro-
vide FIFO status In addition DMA can be used to
transfer data to the FIFO by enabling this feature in
the ECR
Second the data is transferred to the peripheral us-
ing an automatic hardware handshake This hand-
shake emulates the standard ISA-Compatible style
software generated handshake (Figure 45) For ISA-
Compatible FIFO mode the 82091AA does not
monitor the ACK signal Service interrupts are en-
abled and reported via the ECR The generation of
service interrupts is based on the state of the FIFO
and not individual transfers (using ACK ) as is the
case in standard ISA-Compatible mode
Figure 45 ISA-Compatible Timing
290486 – 45
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