82091AA Datasheet, PDF (113/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
Bit
Description
7 DATA CARRIER DETECT STATUS This bit is the compliment of the Data Carrier Detect (DCD )
input If bit 4 of the MCR is set to a 1 this bit is equivalent to IRQ ENABLE in the MCR
6 RING INDICATOR STATUS This bit is the compliment of the Ring Indicator (RI) input If bit 4 of the
MCR is set to a 1 this bit is equivalent to OUT1 in the MCR
5 DATA SET READY STATUS This bit is the compliment of the Data Set Ready (DSR ) input If bit 4
of the MCR is set to a 1 this bit is equivalent to DTR in the MCR
4 CLEAR TO SEND STATUS This bit is the compliment of the Clear to Send (CTS ) input If bit 4 of
the MCR is set to a 1 this bit is equivalent to RTS in the MCR
3 DELTA DATA CARRIER DETECT STATUS This bit is the Delta Data Carrier Detect (DDCD)
indicator Bit 3 indicates that the DCD input to the chip has changed state
NOTE
Whenever bit 0 1 2 or 3 is set to logic 1 a Modem Status Interrupt is generated
2 TRAILING EDGE OF RING INDICATOR STATUS This bit is the Trailing Edge of Ring Indicator
(TERI) detector Bit 2 indicates that the RI input to the chip has changed from a low to a high state
1 DELTA DATA SET READY STATUS This bit is the Delta Data Set Ready (DDSR) indictor Bit 1
indicates that the DSR input to the chip has changed state since the last time it was read by the
CPU
0 DELTA CLEAR TO SEND STATUS This bit is the Delta Clear to Send (DCTS) indicator Bit 0
indicates that the CTS input to the chip has changed state since the last time it was read by the
CPU
7 1 11 SCR(A B) SCRATCHPAD REGISTER
I O Address
Default Value
Attribute
Size
Base ^a7h
00h
Read Write
8 bits
This 8-bit read write register does not control the serial port module in any way It is intended as a scratchpad
register to be used by the programmer to hold data temporarily
Bit
Description
7 0 SCRATCHPAD DATA Bits 7 0 of this register correspond to SD 7 0
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