82091AA Datasheet, PDF (125/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
8 1 6 FDCFIFO FDC FIFO (DATA)
I O Address
Default Value
Attribute
Size
Base ^a5h
00h
Read Write
8 bits
All command parameter information and disk data transfers go through the 16-byte FIFO The FIFO has
programmable threshold values Data transfers are governed by the RQM and DIO bits in the MSR At the start
of a command the FIFO action is always disabled and command parameters must be sent based upon the
RQM and DIO bit settings At the start of the command execution phase the FDC clears the FIFO of any data
to ensure that invalid data is not transferred An overrun or underrun will terminate the current command and
the transfer of data Disk writes complete the current sector by generating a 00 pattern and valid CRC
The FIFO defaults to an 8272A compatible mode after a hardware reset (via RSTDRV pin) Software resets
(via DOR or DSR) can also place the FDC into 8272A compatible mode if the LOCK bit is set to 0 (see the
definition of the LOCK bit) maintaining PC-AT hardware compatibility The default values can be changed
through the CONFIGURE Command (enable full FIFO operation with threshold control) The FIFO provides
the system a larger DMA latency without causing a disk error The following table gives several examples of
the delays with a FIFO The data is based upon the formula Threshold ^c 1 DATA RATE ^c 8 ^b 1 5
ms^eDELAY
FIFO Threshold
1 byte
2 bytes
8 bytes
15 bytes
Maximum Service Delay
(1 Mbps Data Rate)
1 ^c 8 ms ^b 1 5 ms^e6 5 ms
2 ^c 8 ms ^b 1 5 ms^e14 5 ms
8 ^c 8 ms ^b 1 5 ms^e62 5 ms
15 ^c 8 ms ^b 1 5 ms^e118 5 ms
Maximum Delay to Servicing
at 500 Kbps Data Rate
1 ^c 16 ms ^b 1 5 ms^e14 5 ms
2 ^c 16 ms ^b 1 5 ms^e30 5 ms
8 ^c 16 ms ^b 1 5 ms^e126 5 ms
15 ^c 16 ms ^b 1 5 ms^e238 5 ms
Figure 61 FDC FIFO
Bit
Description
7 0 FIFO DATA Bits 7 0 correspond to SD 7 0
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