82091AA Datasheet, PDF (14/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
2 1 Host Interface Signals (Continued)
Signal
Name
Type
Description
DMA SIGNALS
FDDREQ
O FLOPPY DISK CONTROLLER DMA REQUEST The 82091AA asserts FDDREQ
to request service from a DMA controller for the FDC module This signal is
enabled disabled by bit 3 of the Digital Output Register (DOR) When disabled
FDDREQ is tri-stated
FDDACK
I
FLOPPY DISK CONTROLLER DMA ACKNOWLEDGE The DMA controller
asserts this signal to acknowledge the FDC DMA request When asserted the
IORC and IOWC inputs are enabled during DMA transfers This signal is
enabled disabled by bit 3 of the DOR
PPDREQ
O PARALLEL PORT DMA REQUEST Parallel port DMA service request to the
system DMA controller This signal is only used when the parallel port is in ECP
hardware mode and is always negated when the parallel port is not in this mode In
ECP hardware mode DMA requests are enabled disabled by bit 3 of the ECP
Extended Control Register (ECR) When disabled PPDREQ is tri-stated
PPDACK
I
PARALLEL PORT DMA ACKNOWLEDGE The DMA controller asserts this signal
to acknowledge the parallel port DMA request When asserted the IORC and
IOWC inputs are enabled during DMA transfers This signal is enabled disabled
by bit 3 of the ECR Register
TC
I
TERMINAL COUNT The system DMA controller asserts TC to indicate it has
reached the last programmed data transfer TC is accepted only when FDDACK
or PPDACK is asserted
INTERRUPT SIGNALS
IRQ3 IRQ4 O INTERRUPT 3 AND 4 IRQ3 and IRQ4 are associated with the serial ports and
can be programmed (via the AIPCFG2 Register) to be either active high or active
low These signals can be configured for a particular serial channel via hardware
configuration (at powerup) or by software configuration
Under Hardware Configuration
IRQ3 is used as a serial port interrupt if the serial port is configured at address
locations 2F8h–2FFh or 2E8h – 2EFh IRQ4 is used as a serial port interrupt if the
serial port is configured at address locations 3F8h – 3FFh or 3E8h – 3EFh
Under Software configuration
IRQ3 and IRQ4 are independently configured (i e the IRQ does not automatically
track the communication port address assignment)
These interrupts are enabled disabled globally via bit 3 of the serial port Modem
Control Register (MCR) and for specific conditions via the Interrupt Enable
Register (IER) IRQ3 and IRQ4 are tri-stated when not enabled
IRQ5 IRQ7 O INTERRUPT REQUEST 5 IRQ5 and IRQ7 are associated with the parallel port
and can be programmed (via AIPCFG2 Register) to be either active high or active
low Either IRQ5 or IRQ7 is enabled disabled via PCFG1 Register to signal a
parallel port interrupt The interrupt not selected is disabled and tri-stated
During hardware configuration (see Section 4 0 AIP Configuration) IRQ5 is used if
the parallel port is assigned to 278h – 27Fh and IRQ7 is used if the parallel port
interrupt is assigned to either 3BCh – 3BFh or 378h – 37Fh
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