82091AA Datasheet, PDF (82/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
6 1 3 6 TFIFO ECP Test FIFO Register (ECP Mode)
I O Address
Default Value
Attribute
Size
Base ^a400 and (ECR 7 5 ^e110)
UUUU UUUU (undefined)
Read Write
8 bits
The TFIFO Register provides a test mechanism for the ECP mode FIFO Test mode is enabled via the ECR
Register In test mode (ECR 7 5 ^e110) data can be read written or DMAed to from the FIFO by accessing
this register I O address
Data bytes may be read written or DMAed to or from the system to this FIFO in any direction The parallel port
interface signals are not affected by TFIFO accesses and TFIFO data is not transmitted to PD 7 0 The test
FIFO does not stall when overwritten or underrun Data is simply re-written or over-run The full and the empty
bits in the ECR always keep track of the correct FIFO state
The test FIFO transfers data at the maximum ISA rate so that software can generate performance metrics
The FIFO write threshold can be determined by starting with a full TFIFO and emptying it a byte at a time until
a service interrupt is set to 1 in the ECR The FIFO read threshold can be determined by setting the direction
bit in the PCON Register to 1 and filling the FIFO a byte at a time until the service interrupt is set to 1 in the
ECR
NOTE
UeUndefined
290486 – 35
Figure 35 ECP Test FIFO Register (ECP Mode)
Bit
Description
7 0 ECP TEST FIFO Data Bits 7 0 correspond to SD 7 0
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