82091AA Datasheet, PDF (13/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
2 1 Host Interface Signals
Signal
Name
Type
Description
ISA SIGNALS
SA 10 0
I
SYSTEM ADDRESS BUS The 82091AA decodes the standard ISA I O address
space using SA 9 0 SA10 is used along with SA 9 0 to decode the extended
register set of the ECP parallel port SA 10 0 connects directly to the ISA system
address bus
SD 7 0
I O SYSTEM DATA BUS SD 7 0 is a bi-directional data bus Data is written to and
read from the 82091AA on these signal lines SD 7 0 connect directly to the ISA
system data bus
IORC
I
I O READ COMMAND STROBE IORC is an I O access read control signal
When a valid internal address is decoded by the 82091AA and IORC is asserted
data at the decoded address location is driven onto the SD 7 0 signal lines
IOWC
I
I O WRITE COMMAND STROBE IOWC is an I O access write control signal
When a valid internal address is decoded by the 82091AA and IOWC is asserted
data on the SD 7 0 signal lines is written into the decoded address location at the
rising edge of IOWC
NOWS
O NO WAIT-STATES End data transfer signal The 82091AA asserts NOWS when
a valid internal address is decoded by the 82091AA and the IORC or IOWC
signal is asserted This reduces the total bus cycle time by eliminating the wait-
states associated with the default 8-bit I O cycles NOWS is not asserted for IDE
accesses or DMA accesses This is an open drain output pin
IOCHRDY O I O CHANNEL READY The 82091AA uses this signal for parallel port data
transfers when the parallel port is in EPP mode In this case the 82091AA negates
IOCHRDY to extend the cycle to allow for completion of transfers to from the
peripheral attached to the parallel port When the parallel port is in EPP mode the
82091AA negates IOCHRDY to lengthen the ISA Bus cycle if the parallel port BUSY
signal is asserted
The 82091AA also uses IOCHRDY during hardware configuration time (see Section
4 0 AIP Configuration) If IOWC IORC is asserted to the 82091AA during
hardware configuration time the 82091AA negates IOCHRDY until hardware
configuration time is completed This is an open drain output pin
AEN
I
ADDRESS ENABLE AEN is used during DMA cycles to prevent the 82091AA from
misinterpreting DMA cycles from valid I O cycles When negated AEN indicates
that the 82091AA may respond to address and I O commands addressed to the
82091AA When asserted AEN informs the 82091AA that a DMA transfer is
occurring When AEN is asserted and a xDACK signal is asserted the 82091AA
responds to the cycle as a DMA cycle
RSTDRV
I
RESET DRIVE RSTDRV forces the 82091AA to a known state All 82091AA
registers are set to their default state
X1 OSC
I
CRYSTAL1 OSCILLATOR Main clock input signal can be a 24 MHz crystal
connected across X1 and X2 or a 24 MHz TTL level clock input connected to X1
X2
I
CRYSTAL2 This signal pin is connected to one side of the crystal when a crystal
oscillator is used to provide the main clock If an external oscillator clock is
connected to X1 this pin is not used and left unconnected
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