82091AA Datasheet, PDF (116/204 Pages) Intel Corporation – ADVANCED INTEGRATED PERIPHERAL (AIP)

82091AA
FDC Register
Address Access
Base ^a
0h
1h
2h
3h
4h
4h
5h
6h
7h
7h
Table 23 Floppy Disk Controller Registers⁽¹⁾
Abbreviation
Register Name
Access Wakes Up
FDC
SRB
DOR
TDR
MSR
DSR
FIFO
DIR
CCR
Reserved
Status Register B
Digital Output Register
Tape Drive Register
Main Status Register
Datarate Select Register
Data FIFO
Reserved
Digital Input Register
Configuration Control Register
No
No⁽²⁾
No
Yes
No⁽²⁾
Yes
No
Access
RO
RW
RW
RO
WO
RW
RO
WO
NOTES
1 The base address is 3F0h (primary address) or 370 (secondary address)
2 While writing to the DOR or DSR does not wake up the FDC writing any of the motor enable bits in the DOR or invoking
a software reset (either via DOR or DSR reset bits) will wake up the FDC
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