82830MP Datasheet, PDF (97/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
Bit
Descriptions
3
VGA Enable. Controls the routing of CPU initiated transactions targeting VGA compatible I/O and
memory address ranges. When this bit is set, the GMCH-M will forward the following CPU accesses to
the AGP:
1) memory accesses in the range 0A0000h to 0BFFFFh
2) I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh
(inclusive of ISA address aliases - A[15:10] are not decoded)
When this bit is set , forwarding of these accesses issued by the CPU is independent of the I/O address
and memory address ranges defined by the previously defined base and limit registers. Forwarding of
these accesses is also independent of the settings of the bit 2 (ISA Enable) of this register if this bit is 1.
If the VGA enable bit is set, then accesses to IO address range x3BCh-x3BFh are forwarded to Hub
Interface.
If the VGA enable bit is not set then accesses to IO address range x3BCh-x3BFh are treated just like any
other IO accesses, i.e. the cycles are forwarded to AGP if the address is within IOBASE and IOLIMIT and
ISA enable bit is not set, otherwise they are forwarded to Hub Interface.
If this bit is 0, then VGA compatible memory and I/O range accesses are not forwarded to AGP but rather
they are mapped to primary PCI unless they are mapped to AGP via I/O and memory range registers
defined above (IOBASE, IOLIMIT, MBASE, MLIMIT, PMBASE, PMLIMIT)
The following table shows the behavior for all combinations of MDA and VGA:
VGA MDA
Behavior
0
0
All References to MDA and VGA Go To Hub Interface (Default)
0
1
Illegal Combination (DO NOT USE)
1
0
All References To VGA Go To AGP MDA-only references (I/O
Address 3BF and aliases) will go to Hub Interface.
1
1
VGA References Go To AGP; MDA references go to Hub Interface
Default Value=0.
2
ISA Enable: Modifies the response by the GMCH-M to an I/O access issued by the CPU that target ISA
I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT registers.
When this bit is set to 1, GMCH-M will not forward to PCI1/AGP any I/O transactions addressing the last
768 bytes in each 1KB block even if the addresses are within the range defined by the IOBASE and
IOLIMIT registers. Instead of going to PCI1/AGP these cycles will be forwarded to Hub Interface where
they can eventually be subtractive or positively claimed by the ISA bridge. If this bit is “0” (default) then all
addresses defined by the IOBASE and IOLIMIT for CPU I/O transactions will be mapped to PCI1/AGP.
Default Value=0.
1
SERR# Enable. This bit normally controls forwarding SERR# on the secondary interface to the primary
interface. The GMCH-M does not support the SERR# signal on the AGP PCI1 bus. Hardwired to a “0”.
0
Parity Error Response Enable: Controls GMCH-M’s response to data phase parity errors on PCI1/AGP
G_PERR# is not implemented by the GMCH-M. However, when this bit is set to 1, address and data
parity errors on PCI1 are reported via SERR messaging, if enabled by SERRE1. If this bit is reset to 0,
then address and data parity errors on PCI1/AGP are not reported via the GMCH-M SERR# signal. Other
types of error conditions can still be signaled via SERR messaging independent of this bit’s state.
Default Value=0.
298338-001
Datasheet
97