82830MP Datasheet, PDF (90/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
4.5.2.12
SUBUSN - Subordinate Bus Number Register - Device #1
Address Offset:
Default Value:
Access:
Size:
1Ah
00h
Read /Write
8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI1/AGP. This
number is programmed by the PCI configuration software to allow mapping of configuration cycles to
PCI1/AGP.
Bit Descriptions
7:0 Bus Number. Programmable
Default Value=00000000.
4.5.2.13
SMLT - Secondary Master Latency Timer Register - Device #1
Address Offset:
Default Value:
Access:
Size:
1Bh
00h
Read/Write
8 bits
Note:
This register controls the bus tenure of the GMCH-M on AGP/PCI. SMLT is an 8-bit register that
controls the amount of time the GMCH-M, as an AGP/PCI bus master, can burst data on the AGP/PCI
Bus. The Count Value is an 8-bit quantity, however SMLT[2:0] are reserved and assumed to be 0 when
determining the Count Value. The GMCH-M’s SMLT is used to guarantee to the AGP master a
minimum amount of the system resources. When the GMCH-M begins the first PCI bus cycle after
being granted the bus, the counter is loaded and enabled to count from the assertion of FRAME#. If the
count expires while the GMCH-M’s grant is removed (due to AGP master request), then the GMCH-M
will lose the use of the bus, and the AGP master agent may be granted the bus. If GMCH-M’s bus grant
is not removed, the GMCH-M will continue to own the AGP/PCI bus regardless of the SMLT expiration
or idle condition.
The GMCH-M must always properly terminate an AGP/PCI transaction, with FRAME# negation prior
to the final data transfer.
The number of clocks programmed in the SMLT represents the guaranteed time slice (measured in 66-
MHz PCI clocks) allotted to the GMCH-M, after which it must complete the current data transfer phase
and then surrender the bus as soon as its bus grant is removed. For example, if the SMLT is programmed
to 18h, then the value is 24 AGP clocks. The default value of SMLT is 00h and disables this function.
When the SMLT is disabled, the burst time for the GMCH-M is unlimited (i.e. the GMCH-M can burst
forever).
Bit Description
7:3 Secondary MLT counter value.
Default Value=00000.
2:0 Reserved.
90
Datasheet
298338-001