82830MP Datasheet, PDF (43/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
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4.4
4.4.1
Some of the GMCH-M registers described in this section contain reserved bits. These bits are labeled
"Reserved”. Software must deal correctly with fields that are reserved. On reads, software must use
appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of
reserved bit positions must first be read, merged with the new values for other bit positions and then
written back. Note the software does not need to perform read, merge, and write operations for the
configuration address register.
In addition to reserved bits within a register, the GMCH-M contains address locations in the
configuration space of the Host-Hub Interface Bridge entity that are marked either "Reserved" or “Intel
Reserved”. The GMCH-M responds to accesses to “Reserved” address locations by completing the host
cycle. When a “Reserved” register location is read, a zero value is returned. (“Reserved” registers can be
8-, 16-, or 32-bit in size). Writes to “Reserved” registers have no effect on the GMCH-M. Registers that
are marked as “Intel Reserved” must not be modified by system software. Writes to “Intel Reserved”
registers may cause system failure. Reads to “Intel Reserved” registers may return a non-zero value.
Upon Reset, the GMCH-M sets all of its internal configuration registers to predetermined default states.
Some register values at reset are determined by external strapping options. The default state represents
the minimum functionality feature set required to successfully bring up the system. Hence, it does not
represent the optimal system configuration. It is the responsibility of the system initialization software
(usually BIOS) to properly determine the SDRAM configurations, operating parameters and optional
system features that are applicable, and to program the GMCH-M registers accordingly.
I/O Mapped Registers
The GMCH-M contains a set of registers that reside in the CPU I/O address space - the Configuration
Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The
Configuration Address Register enables/disables the configuration space and determines what portion of
configuration space is visible through the Configuration Data window.
CONFIG_ADDRESS - Configuration Address Register
I/O Address:
Default Value:
Access:
Size:
0CF8h Accessed as a Dword
00000000h
Read/Write
32 bits
CONFIG_ADDRESS is a 32-bit register accessed only when referenced as a Dword. A Byte or Word
reference will "pass through" the Configuration Address Register and Hub Interface onto the PCI0 bus
as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function
Number, and Register Number for which a subsequent configuration access is intended.
31 ^{30 24 23 16 15 11 10}
87
2 1 0 Bit
0
R
0
0
0
0
R ^Default
Reserved
Register Number
Function Number
Device Number
Bus Number
Reserved
Enable
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Datasheet
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