82830MP Datasheet, PDF (20/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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3.1
Host Interface Signals
Table 2. Host Interface Signal Descriptions
Signal Name
Type Description
CPURST#
HA[31:3]#
HD[63:0]#
ADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
O
AGTL+
I/O
AGTL+
I/O
AGTL+
I/O
AGTL+
I/O
AGTL+
O
AGTL+
I/O
AGTL+
O
AGTL+
I/O
AGTL+
I/O
AGTL+
I/O
AGTL+
I
AGTL+
I/O
AGTL+
CPU Reset. The CPURST# pin is an output from the GMCH-M. The GMCH-M
asserts CPURST# while RESET# (PCIRST# from ICH3-M) is asserted and for
approximately 1 ms after RESET# is deasserted. The CPURST# allows the
CPUs to begin execution in a known state.
Note that the ICH3-M must provide CPU strap set-up and hold times around
CPURST#. This requires strict synchronization between GMCH-M CPURST#
deassertion and ICH3-M driving the straps.
Host Address Bus: HA[31:3]# connect to the CPU address bus. During CPU
cycles the HA[31:3]# are inputs. The GMCH-M drives HA[31:3]# during snoop
cycles on behalf of hub interface and AGP/Secondary PCI initiators. Note that
the address bus is inverted on the CPU bus.
Host Data: These signals are connected to the CPU data bus. Note that the
data signals are inverted on the CPU bus.
Address Strobe: The CPU bus owner asserts ADS# to indicate the first of
two cycles of a request phase.
Block Next Request: Used to block the current request bus owner from
issuing a new request. This signal is used to dynamically control the CPU bus
pipeline depth.
Priority Agent Bus Request: The GMCH-M is the only Priority Agent on the
CPU bus. It asserts this signal to obtain the ownership of the address bus.
This signal has priority over symmetric bus requests and will cause the current
symmetric owner to stop issuing new transactions unless the HLOCK# signal
was asserted.
Data Bus Busy: Used by the data bus owner to hold the data bus for
transfers requiring more than one cycle.
Defer: GMCH-M will generate a deferred response as defined by the rules of
the GMCH-M’s dynamic defer policy. The GMCH-M will also use the DEFER#
signal to indicate a CPU retry response.
Data Ready: Asserted for each cycle that data is transferred.
Hit: Indicates that a caching agent holds an unmodified version of the
requested line. Also, driven in conjunction with HITM# by the target to extend
the snoop window.
Hit Modified: Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line.
Also, driven in conjunction with HIT# to extend the snoop window.
Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and
ADS#, until the negation of HLOCK# must be atomic, i.e. no hub interface or
AGP/PCI snoopable access to SDRAM is allowed when HLOCK# is asserted
by the CPU.
Host Request Command: Asserted during both clocks of request phase. In
the first clock, the signals define the transaction type to a level of detail that is
sufficient to begin a snoop request. In the second clock, the signals carry
additional information to define the complete transaction type. The
transactions supported by the GMCH-M Host Bridge are defined in the Host
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Datasheet
298338-001