82830MP Datasheet, PDF (52/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
4.5.1.8
MLT - Master Latency Timer Register - Device #0
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
Read Only
8 bits
Hub Interface does not comprehend the concept of a Master Latency Timer. Therefore the functionality
of this register is not implemented and the register is hardwired to 0.
Bit Description
7:0 These bits are hardwired to 0. Writes have no affect.
Default Value=0000/0000.
4.5.1.9
HDR - Header Type Register - Device #0
Address Offset:
Default Value:
Access:
Size:
0Eh
00h
Read Only
8 bits
This register identifies the header layout of the configuration space. No physical register exists at this
location.
Bit Descriptions
7:0 This read only field always returns 0 when read and writes have no affect.
Default Value=0000/0000.
52
Datasheet
298338-001