82830MP Datasheet, PDF (29/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
3.5
Clocking and Reset
Table 10. Clocking and Reset Signal Descriptions
Signal Name Type Description
HTCLK;
HTCLK#
GBOUT
GBIN
GM_GCLK;
GM_RCLK
DCLKREF
RESET#
I
CMOS
O
CMOS
I
CMOS
O
CMOS
I
LVTTL
I
LVTTL
Host Clock In: These pins receive a buffered host clock from the external clock
synthesizer. This clock is used by all of the GMCH-M. The clock is also the reference
clock for the graphics core PLL. This is a low voltage differential input.
AGP/Hub Clock Reference Output: This clock goes to the external AGP/Hub/PCI
buffer.
AGP/Hub Input Clock: 66 MHz, 3.3-V input clock from external buffer AGP/Hub-link
interface.
Reserved
Reserved
Reset In: When asserted, this signal will asynchronously reset the GMCH-M logic.
This signal is connected to the PCIRST# output of the ICH3-M. The ICH3-M drives this
to 3.3V. All AGP/PCI output and bi-directional signals will also tri-state compliant to
PCI rev 2.2 specifications. This input should have a Schmidt trigger to avoid spurious
resets. Note that this input needs to be 3.3-V tolerant.
Total pins for Clocks/Resets section: 8.
298338-001
Datasheet
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