82830MP Datasheet, PDF (42/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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To prepare for mapping of the configuration cycles on AGP/PCI1 the initialization software will go
through the following sequence:
Scan all devices residing on the PCI Bus #0 using Type 0 configuration accesses.
Note:
For every device residing at bus #0 which implements PCI-PCI bridge functionality, it will configure the
secondary bus of the bridge with the appropriate number and scan further down the hierarchy. This
process will include the configuration of the “virtual” PCI-PCI Bridge within the GMCH-M used to map
the AGP address space in a software specific manner.
Although initial AGP platform implementations will not support hierarchical buses residing below AGP,
this specification still must define this capability in order to support PCI-66 compatibility. Note also that
future implementations of the AGP devices may support hierarchical PCI or AGP-like buses coming out
of the root AGP device.
4.2.6
Internal GMCH-M Configuration Register Access Mechanism
Accesses decoded as PCI Bus #0/Device #0 (Host-Hub Interface Bridge/SDRAM Controller) or PCI Bus
#0/Device #1 (Host-AGP Bridge) are sequenced as Type 0 PCI Configuration Cycle accesses on Bus #0
to Device #0/Function #0, Device #1/Function #0. Note that since GMCH-M device #0 and #1 are not
multi-function devices, the function number should always be ‘0’. If the function number is not ‘0’ for
accesses to Device #0 or #1, the GMCH-M will not claim the configuration cycle and it will be
forwarded to the Hub Interface where it should be master aborted (by the ICH3-M) in the same way as
transactions to other unimplemented PCI configuration targets.
4.3
GMCH-M Register Introduction
The GMCH-M contains two sets of software accessible registers, accessed via the Host CPU I/O address
space:
1. Control registers I/O mapped into the CPU I/O space, which control access to PCI and AGP
configuration space (see section entitled I/O Mapped Registers).
Note:
2. Internal configuration registers residing within the GMCH-M that are partitioned into two logical
device register sets (“logical” since they reside within a single physical device). The first register
set is dedicated to Host-Hub Interface Bridge functionality (controls PCI Bus #0 i.e. SDRAM
configuration, other chip-set operating parameters and optional features). The second register
block is dedicated to Host-AGP/PCI1 Bridge functions (controls AGP/PCI1 interface
configurations and operating parameters).
This configuration scheme is necessary to accommodate the existing and future software configuration
model supported by Microsoft* where the Host Bridge functionality will be supported and controlled via
a dedicated specific driver. Virtual PCI-PCI Bridge functionality will be supported via standard PCI bus
enumeration configuration software. The term “virtual” is used to designate that no real physical
embodiment of the PCI-PCI Bridge functionality exists within the GMCH-M, but that GMCH-M’s
internal configuration register sets are organized in this particular manner to create that impression to the
standard configuration software.
The GMCH-M supports PCI configuration space accesses using the mechanism denoted as
Configuration Mechanism #1 in the PCI specification. The GMCH-M internal registers (both I/O
Mapped and Configuration registers) are accessible by the Host CPU. The registers can be accessed as
Byte, Word (16-bit), or Dword (32-bit) quantities, with the exception of CONFIG_ADDRESS that can
only be accessed as a Dword. All multi-byte numeric fields use "little-endian" ordering (i.e., lower
addresses contain the least significant parts of the field).
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Datasheet
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