82830MP Datasheet, PDF (110/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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5.2.4.8
5.2.4.9
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Agents with this cache line will invalidate the line. If this line is in the modified state an implicit write-
back cycle is generated and the GMCH-M snarfs the data.
The GMCH-M generates length=0 Memory Read and Invalidate transactions for hub interface or
AGP/PCI.
Memory Read (Length = 0)
A Memory Read of length zero, MR(0), does not have an associated Data Response. This transaction is
used by the GMCH-M to snoop for the hub interface to system SDRAM, and AGP/PCI snoopable
system SDRAM read accesses. The GMCH-M snoop request policy is identical for hub interface and
AGP/PCI transactions.
Note that the GMCH-M will perform single MR(0) cycles for hub interface reads less than or equal to 32
bytes, for AGP/PCI master reads or read lines directed to System SDRAM The GMCH-M will do
multiple snoop ahead cycles for hub interface burst reads greater than 32 bytes and for AGP/PCI master
burst reads (i.e. memory read multiple) to SDRAM.
Host Initiated Zero-Length R/W Cycles
Streaming SIMD Extension (SSE) new instructions can result in zero-length read and write cycles to the
chipset.
The GMCH-M supports a zero-length processor write cycle by executing a 1 QW write cycle to the
targeted destination with all 8 byte enables turned off. The following destinations for host initiated zero-
length writes are supported:
1. Coherent system memory
2. Aperture mapped to system memory
3. Aperture mapped to graphics memory
4. GMCH-M internal memory-mapped I/O registers
5. PCI (via hub Interface)
6. AGP
The GMCH-M only supports zero-length processor read cycles that target coherent system memory or
AGP/PCI1. When targeting coherent system memory, the GMCH-M forwards the cycle as a 1 QW read
from system SDRAM. The data is returned to the GMCH-M. The GMCH-M then returns a “no data”
response to the host and empties the returned data from its buffer.
Cache Coherency Cycles
The GMCH-M generates an implicit writeback response during host bus read and write transactions
when a CPU asserts HITM# during the snoop phase. The CPU initiated write case has two data transfers,
the requesting agents data followed by the snooping agents writeback data.
The GMCH-M will perform a memory read and invalidate cycle of length = 0 (MRI[0]) on the CPU bus
when a hub interface or AGP/PCI occurs.
The GMCH-M will perform a memory read cycle with length = 0 (MR[0]) on the CPU bus when a hub
interface or AGP/PCI occurs.
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Datasheet
298338-001