82830MP Datasheet, PDF (53/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
4.5.1.10
APBASE - Aperture Base Configuration Register - Device #0
Address Offset:
Default Value:
Access:
Size:
10-13h
00000008h
Read/Write, Read Only
32 bits
The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics
Aperture. The standard PCI Configuration mechanism defines the base address configuration register
such that only a fixed amount of space can be requested (dependent on which bits are hardwired to “0”
or behave as hardwired to “0”).
To allow for flexibility (of the aperture) an additional register called APSIZE is used as a “back-end”
register to control which bits of the APBASE will behave as hardwired to “0”. This register will be
programmed by the GMCH-M specific BIOS code that will run before any of the generic configuration
software is run.
Note that bit 9 of the GCC0 register at 51-50h is used to prevent accesses to the aperture range before the
configuration software initializes this register and the appropriate translation table structure has been
established in the main memory.
Bit
31:28
27:25
Description
Upper Programmable Base Address bits (R/W). These bits are used to locate the range size selected via
lower bits 27:4.
Default Value = 0000.
Lower “Hardwired”/Programmable Base Address bits . These bits behave as a “hardwired” or as a
programmable depending on the contents of the APSIZE register as defined below:
27
26
25
Aperture Sizer/w
r/w
r/w
r/w
32 MB
r/w
r/w
r/w
64 MB
r/w
0
0
128 MB
0
0
0
256 MB
The Default for APSIZE[5:3,0]=0000 with forces default APBASE[27:25] =000 (i.e. all bits respond as
“hardwired” to 0). This provides a default to the maximum aperture size of 256MB. The GMCH-M specific
BIOS is responsible for selecting smaller size (if required) before PCI configuration software runs and
establishes the system address map.
Default Value=000.
24:4 Hardwired to “0”. This forces minimum aperture size selected by this register to be 32 MB.
3
Prefetchable (RO). This bit is hardwired to “1” to identify the Graphics Aperture range as a prefetchable,
i.e. there are no side effects on reads, the device returns all bytes on reads regardless of the byte enables,
and the GMCH-M may merge processor writes into this range without causing errors.
2:1
Type (RO). These bits determine addressing type and they are hardwired to “00” to indicate that address
range defined by the upper bits of this register can be located anywhere in the 32-bit address space.
Default Value=00.
0
Memory Space Indicator (RO). Hardwired to “0” to identify aperture range as a memory range.
298338-001
Datasheet
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