82830MP Datasheet, PDF (55/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
4.5.1.14
RRBAR - Register Range Base Address Register - Device #0
Address Offset:
Default Value:
Access:
Size:
48-4Bh
00000000h
Read/Write, Read Only
32 bits
This register requests a 256-KB allocation for the Device registers. The base address is defined by bits
31 to 18 and can be used to access device configuration registers. Only Dword aligned writes are
allowed to this space. See Table below for address map within the 512-KB space.
This addressing mechanism may be used to write to registers that modify the device address map
(includes all the BARs, PAMs, SMM registers, Pre-Allocated Memory registers etc). However, before
using or allowing the use of the modified address map the BIOS must synchronize using an IO or Read
cycle.
Note that bit 8 of the GCC0 register at 51-50h is used to prevent accesses to this range before the
configuration software initializes this register.
Bit
31:18
17:15
15:8
7:0
Description
Memory Base Address-R/W. Set by the OS, these bits correspond to address signals [31:18].
Default Value=0000/0000/0000/0.
Address Mask-RO. Hardwired to 0s to indicate 512-KB address range. The Minimum size that can be
requested by converting all these bits to R/W would be 64 KB.
Default Value=000.
Reserved. Hardwired to 00h.
Scratch Pad Size-RO, Hardwired to “00h”.
00h = 256B
FFh = 64 KB
Default Value=0000/0000.
Address Range
Sub Ranges
00000h to
3FFFFhDevice 0
Space
00000h to 0003Fh
00040h to 000FFh
00100h to 3FEFFh
3FF00h to 3FFFFh
Description
Read Only: Maps to 00-3Fh of Device #0 P&P register space.
Read/Write: Maps to 40-FFh of Device #0 P&P register space.
Read/Write: Extended Register Space. Reserved.
Scratch Pad Registers: 256 B, D-word read/write-able.
298338-001
Datasheet
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