82830MP Datasheet, PDF (126/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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Thermal Override. The chipset will detect thermal events via an input to the ICH3-M. When a thermal
threshold has been exceeded a thermal sensor will assert a signal to the ICH3-M. If the signal
remains asserted for more than 2 seconds the chipset will initiate thermal throttling. STPCLK#
will be asserted to place the processor into the C2 state with a programmable duty cycle. This
function can be enabled or disabled via a configuration bit. The Thermal Override condition is
handled by the ICH3-M.
Deep Sleep (C3)
The Deep Sleep and Deeper Sleep states are identical as far as the GMCH-M is concerned. The only
difference externally is that the CPU voltage is lowered for Deeper Sleep state to a point where the CPU
will no longer operate, but it will retain its state. It uses a new power savings mode in the mobile Intel
Pentium III Processor-M. The C3 entry and exit sequence is also followed by an Intel SpeedStep
transition. C3 entry will generally occur when the system is idle, and no bus master activity has taken
place recently as indicated by PCI REQ# signals and AGP_BUSY# (although AGP_BUSY# being
active does not guarantee C3 will not be entered). Intel SpeedStep transitions may occur at any time,
while the system is busy and bus master activity is occurring. There will be no attempt to wait for the
system to be idle for an Intel SpeedStep transition.
C3 may be entered even if AGP_BUSY# is active, since there is a delay from the time AGP_BUSY# is
sampled by the OS and C3 is actually entered. AGP_BUSY# does not prevent C3 entry in hardware, it
only indicates to the OS that activity is present. The OS will choose C2 rather than C3 in this case.
AGP_BUSY# active will cause a C3 exit, however, so the C3 mode will be brief if AGP_BUSY# is
active. An Intel SpeedStep transition, which appears to the GMCH-M exactly as a C3 entry/exit, will
occur regardless of the state of AGP_BUSY#
The GMCH-M can assume that no AGP, AGP/PCI, or Hub Interface cycle (except special cycles) will
occur while the GMCH-M is in the C3 state. The processor cannot snoop its caches to maintain
coherency while in the C3 state.
Intel 830MP Chipset AGP_BUSY# Protocol with External
Graphics
The AGP_BUSY# and STP_AGP# signals allow power management signaling between an external
AGP graphics controller and the ICH3-M. AGP_BUSY# indicates that the AGP device is busy.
C3_STAT# (STP_AGP#) is the signal, which used for indicating to the AGP device that a C3 state
transition is beginning or ending. AGP_BUSY# (ICH3-M signal) and STP_AGP# (AGP graphics
controller signal) are not directly connected to the GMCH-M. For proper implementations, please
consult Intel Field Application Engineers
Intel SpeedStep Technology
Intel SpeedStep technology allows the system to operate in multiple performance states Intel SpeedStep
technology define two CPU/system operational modes:
MaximumPerformance Mode: Maximum CPU Core Frequency, requiring a higher CPU Core voltage.
Battery Optimized Mode: Reduced CPU core frequency to extend battery life. Allows for lower CPU
Core voltage for additional power savings.
Intel SpeedStep technology transitions states only when AC power is connected or disconnected. It
transitions by changing the CPU PLL multiplier, which can only be done in the Deep Sleep CPU state
(clock going to the CPU is stopped), which is the C3 CPU power state.
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Datasheet
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