82830MP Datasheet, PDF (50/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
4.5.1.4
PCISTS - PCI Status Register - Device #0
Address Offset:
Default Value:
Access:
Size:
06-07h
0010h
Read Only, Read/Write Clear
16 bits
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s Hub
Interface. Bit 14 is read/write clear. All other bits are Read Only. Since GMCH-M Device #0 is the
host-to-Hub Interface bridge, many of the PCI specific bits in this register don’t apply.
Bit
Description
15
Detected Parity Error (DPE). This bit is hardwired to a 0. Writes to this bit position have no affect.
Default Value=0.
14
Signaled System Error (SSE). This bit is set to 1 when GMCH-M Device #0 generates an SERR
message over Hub Interface for any enabled Device #0 error condition.
Device #0 error conditions are enabled in the PCICMD and ERRCMD registers. Device #0 error flags
are read/reset from the PCISTS or ERRSTS registers.
Software sets SSE to 0 by writing a 1 to this bit.
Default Value=0.
13
Received Master Abort Status (RMAS). This bit is set when the GMCH-M generates a Hub
Interface request that receives a Master Abort completion packet. Software clears this bit by writing a
1 to it.
Default Value=0.
12
Received Target Abort Status (RTAS). This bit is set when the GMCH-M generates a Hub Interface
request that receives a Target Abort completion packet. Software clears this bit by writing a 1 to it.
Default Value=0.
11
Signaled Target Abort Status (STAS). The GMCH-M will not generate a Target Abort Hub Interface
completion packet. This bit is not implemented in the GMCH-M and is hardwired to a 0. Writes to this
bit position have no effect.
Default Value=0.
10:9 DEVSEL# Timing (DEVT). Hub Interface does not comprehend DEVSEL# protocol. These bits are
hardwired to “00”. Writes to these bits have no effect.
Default Value=00.
8
Data Parity Detected (DPD). GMCH-M does not support parity on Hub Interface. This bit is hardwired
to a 0. Writes to this bit position have no effect.
Default Value=0.
7
Fast Back-to-Back (FB2B). Hub Interface does not comprehend PCI Fast Back-to-Back protocol.
This bit is hardwired to 0. Writes to this bit position have no effect.
Default Value=0.
6:5 Reserved.
4
Capability List (CLIST). This bit is hardwired to 1 to indicate to the configuration software that this
device/function implements a list of new capabilities.
A list of new capabilities is accessed via register CAPPTR at configuration address offset 34h.
Register CAPPTR contains an offset pointing to the start address within configuration space of this
device where the Capabilities linked list begins.
Default Value=1.
3:0 Reserved.
50
Datasheet
298338-001