82830MP Datasheet, PDF (65/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
Bit
Description
2
DRAM RAS# to CAS# Delay (tRCD). This bit controls the number of CLKs from a Row Activate
command to a read or write command.
0 = 3 clocks will be inserted between a row activate command and either a read or write command.
1 = 2 clocks will be inserted between a row activate command and either a read or write command.
Default Value=0.
1
Reserved
0
DRAM RAS# Precharge (tRP). This bit controls the number of CLKs for RAS# pre-charge.
0 = 3 clocks of RAS# pre-charge are provided.
1 = 2 clocks of RAS# pre-charge are provided
Default Value=0.
298338-001
Datasheet
65