82830MP Datasheet, PDF (70/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
4.5.1.24
SMRAM - System Management RAM Control Register - Device #0
Address Offset:
Default Value:
Access:
Size:
90h
02h
Read/Write/Lock, Read Only
8 bits
The SMRAM register controls how accesses to Compatible and Extended SMRAM spaces are treated.
The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the OPEN bit
must be reset before the LOCK bit is set.
Bit Description
7
Reserved
6
SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM space SDRAM is made
visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space.
Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time.
When D_LCK is set to a 1, D_OPEN is reset to 0 and becomes read only.
Default Value=0.
5
SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is not accessible to data
references, even if SMM decode is active. Code references may still access SMM space SDRAM. This
will allow SMM software to reference "through" SMM space to update the display even when SMM is
mapped over the VGA range.
Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time.
Default Value=0.
4
SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK,
D_OPEN, G_SMRAME, C_BASE_SEG, GMS, DRB, DRA, H_SMRAM_EN, TSEG_SZ and TSEG_EN
become read only.
GBA[15:0] and GAR[15:0] associated with the SDRAM controller also become read only after D_LCK is
set. D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a Full
Reset. The combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use
the D_OPEN function to initialize SMM space and then use D_LCK to "lock down" SMM space in the
future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if the
program has knowledge of the D_OPEN function.
Default Value=0.
3
Global SMRAM Enable (G_SMRAME). If set to a 1, then Compatible SMRAM functions is enabled,
providing 128 KB of SDRAM accessible at the A0000h address while in SMM (ADS# with SMM
decode).
To enable Extended SMRAM function this bit has be set to 1.
Refer to the section on SMM for more details. Once D_LCK is set, this bit becomes read only.
Default Value=0.
2:0 Compatible SMM Space Base Segment (C_BASE_SEG) (RO). This field indicates the location of
SMM space. "SMM DRAM" is not remapped. It is simply "made visible" if the conditions are right to
access SMM space, otherwise the access is forwarded to Hub Interface.
C_BASE_SEG is hardwired to 010 to indicate that the GMCH-M supports the SMM space at A0000h-
BFFFFh.
Default Value=010.
70
Datasheet
298338-001