82830MP Datasheet, PDF (86/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
4.5.2.3
PCICMD1 - PCI-PCI Command Register - Device #1
Address Offset:
Default Value:
Access:
Size
04-05h
0000h
Read/Write, Read Only
16 bits
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Descriptions
Reserved.
Fast Back-to-Back: Not Applicable-hardwired to 0.
Default Value=0.
SERR Message Enable (SERRE1). This bit is a global enable bit for Device #1 SERR messaging. The
GMCH-M does not have an SERR# signal. The GMCH-M communicates the SERR# condition by sending
an SERR message to the ICH3-M. If this bit is set to a 1, the GMCH-M is enabled to generate SERR
messages over Hub Interface for specific Device #1 error conditions that are individually enabled in the
BCTRL register. The error status is reported in the PCISTS1 register. If SERRE1 is reset to 0, then the
SERR message is not generated by the GMCH-M for Device #1.
NOTE: This bit only controls SERR messaging for the Device #1. Device #0 has its own SERRE bit to
control error reporting for error conditions occurring on Device #0. The two control bits are used in a
logical OR manner to enable the SERR Hub Interface message mechanism.
Default Value=0.
Address/Data Stepping: Not applicable. Hardwired to 0.
Parity Error Enable (PERRE1): PERR# is not supported on AGP/PCI1. Hardwired to 0.
Reserved.
Memory Write and Invalidate Enable: (RO) This bit is implemented as Read Only and returns a value of
“0” when read.
Default Value=0.
Special Cycle Enable: (RO) This bit is implemented as Read Only and returns a value of “0” when read.
Default Value=0.
Bus Master Enable (BME1): (R/W) When the Bus Master Enable is set to “0” (default), AGP Master
initiated FRAME# cycles will be ignored by the GMCH-M resulting in a Master Abort. Ignoring incoming
cycles on the secondary side of the P2P bridge effectively disables the bus master on the primary side.
When Bus Master Enable is set to “1”, AGP Master initiated FRAME# cycles will be accepted by the
GMCH-M if they hit a valid address decode range This bit has no affect on AGP Master originated SBA or
PIPE# cycles.
Default Value=0.
Memory Access Enable (MAE1): (R/W) This bit must be set to “1” to enable the Memory and
Prefetchable memory address ranges defined in the MBASE, MLIMIT, PMBASE, and PMLIMIT registers.
When set to “0” all of device #1’s memory space is disabled.
Default Value=0.
I/O Access Enable (IOAE1): (R/W) This bit must be set to “1” to enable the I/O address range defined in
the IOBASE, and IOLIMIT registers. When set to “0” all of device #1’s I/O space is disabled.
Default Value=0.
86
Datasheet
298338-001