82830MP Datasheet, PDF (62/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
System BIOS Area (F0000h-FFFFFh)
This area is a single 64-KB segment that can be assigned with different attributes via PAM control
register as defined by the Table 21.
4.5.1.19
DRB — DRAM Row Boundary Register - Device #0
Address Offset:
Default Value:
Access:
Size:
60-67h
00h
Read/Write (Read_Only if D_LCK = 1)
8 bits
Row Boundary Register defines the upper boundary address of each SDRAM row in 32-MB granularity.
Each row has its own DRB register. Contents of these 8-bit registers represent the boundary address in
32-MB granularity. For example, a value of 1 indicates 32 MB.
Row0: 60h
Row1: 61h
Row2: 62h
Row3: 63h
Row4: 64h: Reserved
Row5: 65h: Reserved
Row6: 66h: Reserved
Row7: 67h: Reserved
DRB0 = Total memory in row0 (in 32 Mbytes)
DRB1 = Total memory in row0 + row1 (in 32 Mbytes)
----
Note:
DRB4 = Total memory in row0 + row1 + row2 + row3 + (in 32 Mbytes)
The number of DRB registers and number of bits per DRB register are system dependent. For example, a
system that support 4 rows of SDRAM and a max memory of 1.0 GB needs only 4 DRB registers and 4
bits per DRB.
GMCH-M supports 4 physical rows of Single data rate SDRAM in 2 SO-DIMMs. The width of a row is
64 bits. Each SO-DIMM/Row is represented by a byte. Each byte has the following format.
GMCH-M supported maximum memory size: 1.0 GB.
Bit Description
7:0 SDRAM Row Boundary Address: This 8-bit value defines the upper and lower addresses for each
SDRAM row.
Bits 6:0 of this field are compared against the address lines A[31:25] to determine the upper address
limit of a particular row.
Bit 7 must be Zero.
Default Value=0000/0000.
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Datasheet
298338-001