82830MP Datasheet, PDF (128/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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5.5.9
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5.7.1.1
GMCH-M Thermal Management
GMCH-M contains a bandwidth monitor on the SDRAM interfaces. If the bandwidth exceeds a
programmed amount, the GMCH-M will automatically stall to avoid thermal problems.830MP.
Intel will provide a CMTI software suite to profile system for optimal thermal management. Please
contact local FAE for support.
System Bandwidth Monitoring and Throttling
The GMCH-M has the capability for bandwidth monitoring/throttle mechanism for the system memory
interface. If the counter window exceeds the bandwidth threshold, then the SDRAM throttling
mechanism will be invoked to limit the memory reads/writes to a lower bandwidth.
The bandwidth monitoring mechanism consists of a counter to measure SDRAM bandwidth being used.
Depending on what is being monitored, reads, and writes or both, a counter is incremented. If the
number of read/writes during the monitoring period exceeds the value programmed, the throttling
mechanism is invoked.
If GMCH-M detects an idle cycle where no traffic is encountered during the throttling window, the
counter decrements and no throttling takes place. Once the bandwidth reaches the determined
bandwidth, the Intel 830MP chipset will start to throttle and continue throttling determined by the
activity percentage. If the bandwidth never exceeds the set value, no throttling will take place. 830MP
will exit the throttling mechanism and return to monitoring traffic where the process starts over again.
Clocking
GMCH-M has the following clocks:
• 133-MHz Low voltage Differential HTCLK(#) for Processor Side Bus
• 66.666-MHz 3.3V GBOUT Output Clock for external Hub/AGP/PCI buffer
• 66.666-MHz 3.3V GBIN from external buffer for AGP/Hub interface
XOR Test Chains
Another feature of the 830MP chipset is the support for XOR Chain test modes. The XOR Chain test
mode is used by product engineers during manufacturing and OEMs during board level connectivity
tests. The main purpose of this test mode is to detect connectivity shorts between adjacent pins and to
check proper bonding between I/O pads and I/O pins. There are 11 XOR test chains built into the 830MP
chipset.
Test Mode Entry
Excluding the RAC chain, all that is required to prepare the GMCH-M for XOR chain testing is to pull
DVOA_D[7] and G_PAR/ADD_DETECT high prior to deasserting PCIRST#. The following event
sequence will put the GMCH-M into XOR testability mode:
1. Deassert PCIRST# high, deassert DVOA_D[11;8:6;4:3] low, assert G_PAR/ADD_DETECT high
2. Assert PCIRST# low; assert DVOA_D[7:6] high and maintain G_PAR/ADD_DETECT high
3. Deassert PCIRST# high
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Datasheet
298338-001