82830MP Datasheet, PDF (116/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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Table 30. Address Translation and Decoding
Address Usage
Tech Depth Width
Row Col Bank
Row
Size
Page BS BS MA MA MA MA MA MA MA MA MA MA MA MA MA
1 0 12 11 10 9 8 7 6 5 4 3 2 1 0
64 Mb 4M
16 12 8
2 32 MB 2K 12 11 X 15 14 13 24 23 22 21 20 19 18 17 16
12 11 X X PA X X 10 9 8 7 6 5 4 3
128 Mb 8M
16 12 9
2 64 MB 4K 13 12 X 15 14 25 24 23 22 21 20 19 18 17 16
13 12 X X PA X 11 10 9 8 7 6 5 4 3
256 Mb 16M 16
13 9
2 128 MB 4K 13 12 15 14 26 25 24 23 22 21 20 19 18 17 16
13 12 X X PA X 11 10 9 8 7 6 5 4 3
512 Mb 16M 16 13 10 2 256 MB 8K 14 13 15 27 26 25 24 23 22 21 20 19 18 17 16
14 13 X X PA 12 11 10 9 8 7 6 5 4 3
5.3.4
5.4
SDRAM Performance Description
The overall SDRAM performance is controlled by the SDRAM timing register, pipelining depth used in
the Intel 830MP chipset, SDRAM speed grade, and the type of SDRAM used in the system. Besides
this, the exact performance in a system is also dependent on the total memory supported, external
buffering and memory array layout. The most important contribution to overall performance by the
System Memory controller is to minimize the latency required to initiate and complete requests to
memory, and to support the highest possible bandwidth (full streaming, quick turn-arounds). One
measure of performance is the total flight time to complete a cache line request. A true discussion of
performance really involves the entire chipset, not just the System Memory controller.
AGP Interface
The GMCH-M will support 1.5V AGP 1x/2x/4x devices. The AGP signal buffers will have one mode of
operation; 1.5V drive/receive (not 3.3V tolerant). The GMCH-M will support 4x (266MT/s) clocking
transfers for read and write data, and sideband addressing. The GMCH-M has a 32-deep AGP request
queue. The GMCH-M integrates a fully associative 16 entry Translation Look-aside Buffer.
AGP semantic transactions to system SDRAM do not get snooped and are therefore not coherent with
the CPU caches. PCI semantic transactions on AGP to system SDRAM are snooped. AGP semantic
accesses to hub interface/PCI are not supported. PCI semantic access from an AGP master to hub
interface is not supported.
116
Datasheet
298338-001