82830MP Datasheet, PDF (109/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
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5.2.4
5.2.4.1
5.2.4.2
5.2.4.3
5.2.4.4
5.2.4.5
5.2.4.6
5.2.4.7
Host Bus Cycles
The following transaction descriptions illustrate the various operations in their most straightforward
representation. The diagrams do not attempt to show the transaction phase relationships when multiple
transactions are active on the CPU bus. For a full description of the CPU Bus functionality please refer
to the P6 External Bus Specification, Revision 3.0 and Addendum to P6 External Bus Specification Rev
3.1.
Partial Reads
Partial Read transactions include: I/O reads and memory read operations of less than or equal to eight
bytes (four consecutive bytes for I/O) within an aligned 8-byte span. The byte enable signals, BE#[7:0],
select which bytes in the span to read.
Part-Line Read and Write Transactions
The GMCH-M does not support a part-line, i.e. 16-byte transactions.
Cache Line Reads
A read of a full cache line (as indicated by the LEN[1:0]=10 during request phase) requires 32 bytes of
data to be transferred, which translates into four data transfers for a given request. If selected as a target,
the GMCH-M will determine if the address is directed to system SDRAM, hub interface, or AGP/PCI,
and provide the corresponding command and control to complete the transaction.
Partial Writes
Partial Write transactions include: I/O and memory write operations of eight bytes or less (maximum of
four bytes for I/O) within an aligned 8-byte span. The byte enable signals, BE#[7:0], select which bytes
in the span to write. I/O writes crossing a 4-byte boundary are broken into two separate transactions by
the CPU.
Cache Line Writes
A write of a full cache line requires 32 bytes of data to be transferred, which translates into four data
transfers for a given request.
Memory Read and Invalidate (Length > 0)
A Memory Read and Invalidate (MRI) transaction is functionally equivalent to a cache line read. The
purpose this special transaction is to support write allocation (write miss case) of cache lines in the
processors. When a processor issues an MRI, the cache line is read as in a normal cache line read
operation; however, all other caching agents must invalidate this line if they have it in a shared or
exclusive state. If a caching agent has this line in the Modified State, then it must be written back to
memory and invalidated. The GMCH-M snarfs the write-back data.
Memory Read and Invalidate (Length = 0)
A Memory Read and Invalidate transaction of length zero, MRI(0) does not have an associated Data
Response. Executing the transaction will inform other agents in the system that the agent issuing this
request wants exclusive ownership of a cache line that is in the Shared State (write hit to a shared line).
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Datasheet
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