82830MP Datasheet, PDF (78/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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4.5.1.31
AGPCTRL - AGP Control Register - Device #0
Address Offset:
Default Value:
Access:
Size:
B0-B1h
00000000h
Read/Write
32 bits
This register provides for additional control of the AGP interface.
Bit
Description
31:8 Reserved
7
GTLB Enable (and GTLB Flush Control) (R/W):
Note: This bit can be changed dynamically (i.e. while an access to GTLB occurs).
Default Value=0.
6:0 Reserved
4.5.1.32
AFT – AGP Functional Test Register – Device #0
Address Offset: B2-B3h
Default Value:
0000h
Access: Read/Write
Size:
16 bits
This register provides for additional control of the AGP interface.
Bit
15:10
9
8:4
3:0
Description
Reserved
PCI Read Buffer Disable. (RW) When set to “1” is disabled. In this mode all data pre-fetched and
buffered for a PCI-to-DRAM read will be discarded when that read transaction terminates.
This bit defaults to “0”.
AGP PCI1 Discard Timer Time-out Count. (RW) These bits control the length of AGP/PCI1
Delayed Transaction discard time-out for the purpose of enhancing the system testability.
Default value is 11111b (31d) for a discard count of 1024d ((value+1)*32).
Reserved
4.5.1.33
APSIZE Aperture Size - Device #0
Address Offset:
Default Value:
Access:
Size:
B4h
00h
Read/Write
8 bits
This register determines the effective size of the Graphics Aperture. This register can be updated by the
GMCH-M-specific BIOS configuration sequence before the PCI standard bus enumeration sequence. If
the register is not updated then a default value will select an aperture of maximum size (i.e. 256 MB).
The size of the table that will correspond to a 256 MB aperture is not practical for most applications and
78
Datasheet
298338-001