82830MP Datasheet, PDF (91/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
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4.5.2.14
IOBASE - I/O Base Address Register - Device #1
Address Offset:
Default Value:
Access:
Size:
1Ch
F0h
Read/Write
8 bits
This register control the CPU to PCI1/AGP I/O access routing based on the following formula:
IO_BASE=< address =<IO_LIMIT
Note:
Only upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are treated
as 0. Thus the bottom of the defined I/O address range will be aligned to a 4-KB boundary.
BIOS must not set this register to 00h otherwise 0CF8h/0CFCh accesses will be forwarded to AGP.
Bit Description
7:4 I/O Address Base. Corresponds to A[15:12] of the I/O address.
Default Value=1111.
3:0 I/O Addressing Capability. Hardwired to 0h indicating that only 16 bit I/O addressing is supported. Bits
[31:16] of the I/O base address is assumed to be 0000h.
Default Value=0000.
4.5.2.15
IOLIMIT - I/O Limit Address Register - Device #1
Address Offset:
Default Value:
Access:
Size:
1Dh
00h
Read/Write
8 bits
This register controls the CPU to PCI1/AGP I/O access routing based on the following formula:
IO_BASE=< address =<IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are
assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-KB aligned
address block.
Bit Description
7:4 I/O Address Limit. Corresponds to A[15:12] of the I/O address.
Default Value=0000.
3:0 Reserved. (Only 16 bit addressing supported.)
298338-001
Datasheet
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