82830MP Datasheet, PDF (95/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
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4.5.2.19
PMBASE - Prefetchable Memory Base Address Register - Device #1
Address Offset:
Default Value:
Access:
Size:
24-25h
FFF0h
Read/Write
16 bits
This register controls the CPU to PCI1 prefetchable memory accesses routing based on the following
formula:
PREFETCHABLE_MEMORY_BASE=< address =<PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes when read. The
configuration software must initialize this register. For the purpose of address decode, address bits
A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a
1-MB boundary.
Bit
15: 4
3:0
Description
Prefetchable Memory Address Base (PMEM_BASE). Corresponds to A[31:20] of the memory
address.
Default Value=1111/1111/1111.
Reserved.
4.5.2.20
PMLIMIT - Prefetchable Memory Limit Address Register - Device #1
Address Offset:
Default Value:
Access:
Size:
26-27h
0000h
Read/Write
16 bits
This register controls the CPU to PCI1 prefetchable memory accesses routing based on the following
formula:
PREFETCHABLE_MEMORY_BASE=< address =<PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes when read. The
configuration software must initialize this register. For the purpose of address decode, address bits
A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top
of a 1-MB aligned memory block.
Bit
15: 4
3:0
Description
Prefetchable Memory Address Limit (PMEM_LIMIT).Corresponds to A[31:20] of the memory
address.
Default Value=0000/0000/0000.
Reserved.
298338-001
Datasheet
95