82830MP Datasheet, PDF (44/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
Bit
31
30:24
23:16
15:11
10:8
7:2
1:0
Descriptions
Configuration Enable (CFGE). When this bit is set to 1, accesses to PCI configuration space are
enabled. If this bit is reset to 0, accesses to PCI configuration space are disabled.
Reserved (These bits are read only and have a value of 0).
Bus Number. When the Bus Number is programmed to 00h the target of the Configuration Cycle is
either the GMCH-M or the ICH3-M. The Configuration Cycle is forwarded to hub interface if the Bus
Number is programmed to 00h and no device internal to the GMCH-M is the target. If the Bus Number is
non-zero and matches the value programmed into the SECONDARY BUS NUMBER Register of the
AGP/PCI1 bridge, a Type 0 PCI configuration cycle will be generated on AGP/PCI1. If the Bus Number is
non-zero, greater than the value in the SECONDARY BUS NUMBER register of the AGP/PCI1 bridge,
and less than or equal to the value programmed into the SUBORDINATE BUS NUMBER Register, a
Type 1 PCI configuration cycle will be generated on AGP/PCI1. If the Bus Number is non-zero, and is
less than the value programmed into the SECONDARY BUS NUMBER Register of the AGP/PCI1 bridge,
or is greater than the value programmed into the SUBORDINATE BUS NUMBER Register, a Type 1 hub
interface Configuration Cycle is generated.
Device Number. This field selects one agent on the PCI bus selected by the Bus Number. When the Bus
Number field is “00” the GMCH-M decodes the Device Number field. The GMCH-M is always Device #0
for the Host-hub interface bridge entity, and Device #1 for the Host-AGP/PCI1 entity. Therefore, when
the Bus Number = 0 and the Device Number = 0, 1, the internal GMCH-M devices are selected. If the
Bus Number is non-zero and matches the value programmed into the SECONDARY BUS NUMBER
Register of the AGP/PCI1 bridge, a Type 0 PCI configuration cycle will be generated on AGP/PCI1. The
Device Number field is decoded and the GMCH-M asserts one and only one GADxx signal as an IDSEL.
GAD11 is asserted to access Device #0, GAD12 for Device #1, and so forth up to Device #20 for which
will assert GAD31. All device numbers higher than 20 cause a type 0 configuration access with no IDSEL
asserted, which will result in a Master Abort reported in the GMCH-M’s “virtual” PCI-PCI bridge registers.
For Bus Numbers resulting in AGP/PCI1 Type 1 Configuration cycles the Device Number is propagated
as GAD[15:11].
Function Number. This field is mapped to GAD[10:8] during AGP/PCI1 Configuration cycles. This allows
the configuration registers of a particular function in a multi-function device to be accessed. The GMCH-
M ignores configuration cycles to Devices 1 if the function number is not equal to 0.
Register Number. This field selects one register within a particular Bus, Device, and Function as
specified by the other fields in the Configuration Address Register. This field is mapped to GAD[7:2]
during AGP/PCI1 Configuration cycles.
Reserved.
44
Datasheet
298338-001