82830MP Datasheet, PDF (59/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
4.5.1.18
PAM(6:0) - Programmable Attribute Map Registers - Device #0
Address Offset:
Default Value:
Attribute:
Size:
59 - 5Fh
00h
Read/Write
4 bits/register, 14 registers
The GMCH-M allows programmable memory attributes on 13 Legacy memory segments of various
sizes in the 640 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers are
used to support these features. Cacheability of these areas is controlled via the MTRR registers in the P6
processor. Two bits are used to specify memory attributes for each memory segment. These bits apply to
both host, AGP/PCI and Hub Interface initiator accesses to the PAM areas. These attributes are:
RE - Read Enable. When RE = 1, the CPU read accesses to the corresponding memory segment are
claimed by the GMCH-M and directed to main memory. Conversely, when RE = 0, the host read
accesses are directed to PCI0.
WE - Write Enable. When WE = 1, the host write accesses to the corresponding memory segment are
claimed by the GMCH-M and directed to main memory. Conversely, when WE = 0, the host write
accesses are directed to PCI0.
The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or
disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only.
Each PAM Register controls two regions, typically 16 KB in size. Each of these regions has a 4-bit field.
The 4 bits that control each region have the same encoding and are defined in the following table.
Table 20. Attribute Bit Assignment
Bits [7, 3]
Reserved
Bits [6, 2]
Reserved
Bits [5, 1]
WE
Bits [4, 0]
RE
Description
X
X
0
0
Disabled. SDRAM is disabled and all accesses are
directed to Hub Interface. The GMCH-M does not
respond as a AGP/PCI or Hub Interface target for any
read or write access to this area.
X
X
0
1
Read Only. Reads are forwarded to SDRAM and
writes are forwarded to Hub Interface for termination.
This write protects the corresponding memory
segment. The GMCH-M will respond as a AGP/PCI
or Hub Interface target for read accesses but not for
any write accesses.
X
X
1
0
Write Only. Writes are forwarded to SDRAM and
reads are forwarded to the Hub Interface for
termination. The GMCH-M will respond as an
AGP/PCI or Hub Interface target for write accesses
but not for any read accesses.
X
X
1
1
Read/Write. This is the normal operating mode of
main memory. Both read and write cycles from the
host are claimed by the GMCH-M and forwarded to
SDRAM. The GMCH-M will respond as a AGP/PCI or
Hub Interface target for both read and write
accesses.
298338-001
Datasheet
59