82830MP Datasheet, PDF (5/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
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4.5.2.17
4.5.2.18
4.5.2.19
4.5.2.20
4.5.2.21
4.5.2.22
MBASE - Memory Base Address Register - Device #1 ..................93
MLIMIT - Memory Limit Address Register - Device #1 ...................93
PMBASE - Prefetchable Memory Base Address Register - Device
#1 ...................................................................................................95
PMLIMIT - Prefetchable Memory Limit Address Register - Device
#1 ...................................................................................................95
BCTRL - PCI-PCI Bridge Control Register - Device #1 ..................96
ERRCMD1 - Error Command Register - Device #1.......................98
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Functional Description ................................................................................................................99
5.1 System Address Map.....................................................................................................99
5.1.1
System Memory Address Ranges ...............................................................99
5.1.2
Compatibility Area......................................................................................101
5.1.2.1 DOS Area (00000h-9FFFFh) ........................................................102
5.1.2.2 Legacy VGA Ranges (A0000h-BFFFFh) ......................................102
5.1.2.3 Compatible SMRAM Address Range (A0000h-BFFFFh) .............102
5.1.2.4 Monochrome Adapter (MDA) Range (B0000h - B7FFFh) ............102
5.1.2.5 Expansion Area (C0000h-DFFFFh) ..............................................103
5.1.2.6 Extended System BIOS Area (E0000h-EFFFFh) .........................103
5.1.2.7 System BIOS Area (F0000h-FFFFFh) ..........................................103
5.1.3
Extended Memory Area .............................................................................103
5.1.3.1 Main System SDRAM Address Range (0010_0000h to Top of Main
Memory) ........................................................................................103
5.1.3.1.1 15 MB-16 MB Window ................................................104
5.1.3.1.2 Pre-allocated Memory.................................................104
5.1.3.2 Extended SMRAM Address Range (HSEG and TSEG) ...............104
5.1.3.2.1 HSEG ..........................................................................104
5.1.3.2.2 TSEG ..........................................................................104
5.1.3.3 PCI Memory Address Range (Top of Main Memory to 4 GB) ......104
5.1.3.4 Configuration Space (FEC0_0000h -FECF_FFFFh, FEE0_0000h-
FEEF_FFFFh) ...............................................................................105
5.1.3.5 High BIOS Area (FFE0_0000h -FFFF_FFFFh) ............................105
5.1.4
AGP Memory Address Ranges..................................................................105
5.2 Host Interface...............................................................................................................106
5.2.1
Overview ....................................................................................................106
5.2.2
Intel Pentium III Processor-M Unique PSB Activity ...................................106
5.2.3
Host Addresses Above 4 GB .....................................................................108
5.2.4
Host Bus Cycles.........................................................................................109
5.2.4.1 Partial Reads.................................................................................109
5.2.4.2 Part-Line Read and Write Transactions........................................109
5.2.4.3 Cache Line Reads.........................................................................109
5.2.4.4 Partial Writes.................................................................................109
5.2.4.5 Cache Line Writes.........................................................................109
5.2.4.6 Memory Read and Invalidate (Length > 0) ...................................109
5.2.4.7 Memory Read and Invalidate (Length = 0) ...................................109
5.2.4.8 Memory Read (Length = 0) ...........................................................110
5.2.4.9 Host Initiated Zero-Length R/W Cycles.........................................110
5.2.4.10 Cache Coherency Cycles..............................................................110
5.2.4.11 Interrupt Acknowledge Cycles ......................................................111
5.2.4.12 Locked Cycles ...............................................................................111
5.2.4.12.1 CPU<->System SDRAM Locked Cycles ....................111
5.2.4.12.2 CPU<->Hub Interface Locked Cycles .........................111
5.2.4.12.3 CPU<->AGP/PCI Locked Cycles ................................111
5.2.4.13 Branch Trace Cycles.....................................................................111
298338-001
Datasheet
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