82830MP Datasheet, PDF (127/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
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Most of the control for Intel SpeedStep technology is done in the ICH3-M. However, the GMCH-M
must cooperate on certain functions.
Intel 830MP Chipset System “S” States
Powered-On-Suspend (POS) (S1)
The deepest level of power savings that can be achieved by only shutting down clocks occurs in the S1
State. The only clock remaining active in the system in the S1 State is the RTC clock. This clock is used
to detect wake events and to run the hardware in the resume well in the ICH3-M used to reactivate the
system.
During the S1 State the CPU and GMCH-M power is on, however there is no activity, so the only power
consumed is the leakage power. The Clock synthesizer is powered off, this shuts the clocks off in the
Host, Memory, and I/O clock groups.
Suspend-To-RAM (STR) (S3)
The final level of power savings for the GMCH-M is achievable when the Host Clock, Memory Group,
and I/O clock group clocks are shutdown and the GMCH-M is powered down. This occurs when the
system transitions to the S3 state. During transition to the S3 state, first the STPCLK# is asserted and the
Stop Grant cycle snooped by the GMCH-M and forwarded over Hub interface where it is received by the
ICH3-M. At this point the GMCH-M is functioning in the C2 State. The GMCH-M places all of the
SDRAM components into the self-refresh mode. After the GMCH-M has placed all of the SDRAM
components in self refresh, it is safe to enter the STR State. The ICH3-M will then assert a signal,
SLP_S1#, to the clock synthesizer to shutdown all of the clocks in the Host and Memory Clock Groups.
The GMCH-M will assume that no AGP, AGP/PCI, or hub interface cycle (except special cycles) will
occur while the GMCH-M is in the C3 State. The processor cannot snoop its caches to maintain
coherency while in the C3 State.
GMCH-M contains no isolation circuitry and MUST be powered down once STR is reached. If GMCH-
M is powered up and driving outputs to devices that are powered down, component damage will result.
S4 (SUSPEND TO DISK), S5 (Soft Off) State
The Intel 830MP chipset does not distinguish between Suspend to Ram (S3), Suspend to Disk (S4) and
Soft Off (S5) states. From the 830MP perspective, entry and exit to S4 or S5 states, is the same as entry
and exit to S3 state.
System Memory Dynamic CKE support
To reduce EMI and preserve battery life, clocks to unpopulated SO-DIMMs are turned off. The DRB
registers are read to determine if the row is populated. Clocks are turned off in pairs because
SM_CLK[1:0] go to one SO-DIMM, SM_CLK[3:2] go to another SO-DIMM.. The main memory
SDRAMs are power managed during normal operation and in low power modes. Each row has a
separate CKE (clock enable) pin that is used for power management. CKE is used to put the SDRAM
rows into power down mode. Active power management is employed during normal operation. The
memory setting is determined by the thermals of the system and the number of chips in a row. Following
refresh, all SDRAMs are powered down except the one for which there is the first pending request, if
any.
298338-001
Datasheet
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