82830MP Datasheet, PDF (68/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
4.5.1.23
DTC - DRAM Throttling Control Register - Device #0.
Offset Address:
Default Value:
Access:
Size:
8C-8Fh
0000_0000h
Read/Write/Lock
32 bits
Throttling is independent for Reads and Writes. If the number of Oct-Words (16 bytes) read/written
during a global dram sampling window (GDSW) exceeds the DRAM Bandwidth Threshold defined
below, then the DRAM throttling mechanism will be invoked to limit DRAM reads/writes to a lower
bandwidth checked and throttled over smaller time windows. After exceeding the limit, throttling will
be active for the remainder of the current GDSW and for the next GDSW after which it will return to
non-throttling mode. The throttling mechanism accounts for the actual bandwidth consumed during the
sampling window, by reducing the allowed bandwidth within the smaller throttling window based on the
bandwidth consumed during the sampling period.
Bandwidth
Limit
Range within GDSW (as a %age of GDSW) where
Bandwidth Exceeded the Limit
74%
60%
46%
36%
88 - 100%
74 - 88%
88 - 100%
74 - 88%
60 - 74%
82 - 100%
64 - 82%
46 - 64%
84 - 100%
66 – 84%
50 – 66%
36 – 50%
Bandwidth Allowed for rest of current,
next GDSW
(% of Adaptive throttle Window)
68%
60%
54%
48%
44%
38%
34%
30%
32%
28%
26%
24%
Bits
31
30
29:28
Description
Throttle Lock (TLOCK): This bit secures the SDRAM throttling control register. Once a ‘1’ is written to
this bit, all of the configuration register bits in DTC (including TLOCK) documented below become read-
only.
Default Value=0.
Intel Reserved
DRAM Throttle Mode (TMODE):
Bits Mode
0 0 Throttling turned off.
0 1 Bandwidth Counter mechanism is enabled. When bandwidth exceeds threshold set in the r/w PTC
field, DRAM read/write throttling begins.
1 0 Thermal Sensor based throttling enabled. When the device’s thermal sensor is tripped DRAM
68
Datasheet
298338-001