82830MP Datasheet, PDF (37/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

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Figure 2. Logical Bus Structure During PCI Configuration
AGP/PCI1
82830MP
GMCH-M
AGP Bridge
Device #1
Hub I/F Bridge
DRAM Controller
Device #0
Intel^® 830MP Chipset
PCI Bus #0 Hub Interface
LPC Bridge
Device #31
ICH3-M
PCI Bridge
Device #30
PCI0
LAN Controller
Device #8
4.2
Routing Configuration Accesses to PCI0 or AGP/PCI
The GMCH-M supports two bus interfaces: Hub Interface and AGP/PCI. PCI configuration cycles are
selectively routed to both interfaces. The GMCH-M is responsible for routing PCI configuration cycles
to the proper interface. PCI configuration cycles to ICH3-M internal devices and Primary PCI (including
downstream devices) are routed to the ICH3-M via Hub Interface. AGP/PCI1 configuration cycles are
routed to AGP. The AGP/PCI1 interface is treated as a separate PCI bus from the configuration point of
view. Routing of configuration accesses to AGP/PCI1 is controlled via the standard PCI-PCI bridge
mechanism using information contained within the PRIMARY BUS NUMBER, the SECONDARY
BUS NUMBER, and the SUBORDINATE BUS NUMBER registers of the Host-AGP/PCI1 (device #1).
298338-001
Datasheet
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