82830MP Datasheet, PDF (9/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
Tables
Table 1. Signal Voltage Levels ...................................................................................................19
Table 2. Host Interface Signal Descriptions ...............................................................................20
Table 3. System Memory Interface Signal Descriptions.............................................................22
Table 4. AGP Addressing Signal Descriptions ...........................................................................23
Table 5. AGP Flow Control Signal Descriptions .........................................................................24
Table 6. AGP Status Signal Descriptions ...................................................................................24
Table 7. AGP Clock Signal-Strobe Descriptions ........................................................................25
Table 8. PCI Signals – AGP Semantics Signal Descriptions .....................................................26
Table 9. Hub Interface Signal Descriptions ................................................................................28
Table 10. Clocking and Reset Signal Descriptions ....................................................................29
Table 11. Graphics Memory Interface Signal Descriptions ........................................................30
Table 12. Dedicated Digital Video Port (DVOA) Signal Descriptions.........................................31
Table 13. Analog Display Signal Descriptions............................................................................32
Table 14. Display Control Signal Descriptions ...........................................................................33
Table 15. Voltage References, PLL Power Signal Descriptions ................................................34
Table 16. Strap Signal Descriptions ...........................................................................................35
Table 17. AGP/PCI1 Config Address Remapping......................................................................41
Table 18. Nomenclature for Access Attributes ...........................................................................45
Table 19. Host-Hub I/F Bridge/SDRAM Controller Configuration Space (Device #0)................46
Table 20. Attribute Bit Assignment .............................................................................................59
Table 21. PAM Registers and Associated Memory Segments ..................................................61
Table 22. Summary of GMCH-M Error Sources, Enables and Status Flags .............................74
Table 23. Host-AGP Bridge Configuration Space (Device #1)...................................................84
Table 24. Memory Segments and Attributes ............................................................................102
Table 25. Host Bus Transactions Supported by GMCH-M.......................................................107
Table 26. Host Bus Responses Supported by GMCH-M .........................................................108
Table 27. GMCH-M Responses to Host Initiated Special Cycles ............................................112
Table 28. System Memory SO-DIMM Configurations ..............................................................114
Table 29. Data Bytes on SO-DIMM Used for Programming SDRAM Registers ......................115
Table 30. Address Translation and Decoding ..........................................................................116
Table 31. AGP Commands Supported by GMCH-M When Acting as an AGP Target ............117
Table 32. PCI Commands Supported by GMCH-M When Acting as a PCI Target .................120
Table 33. PCI Commands Supported by GMCH-M When Acting as an AGP/PCI1 Initiator ...121
Table 34. Intel 830MP Chipset System and CPU States .........................................................125
Table 35. RAC Chain Timing Descriptions ...............................................................................130
Table 36. XOR Chain Differential Pairs ....................................................................................131
Table 37. NC Ball and Associated XOR Chain ........................................................................133
Table 38. XOR Chain AGP1.....................................................................................................134
Table 39. XOR Chain AGP2.....................................................................................................135
Table 40. XOR Chain DVO.......................................................................................................136
Table 41. XOR Chain PSB1 .....................................................................................................136
Table 42. XOR Chain PSB2 .....................................................................................................138
Table 43. XOR Chain GPIO .....................................................................................................140
Table 44. XOR Chain HUB .......................................................................................................140
Table 45. XOR Chain SM1 .......................................................................................................141
Table 46. XOR Chain SM2 .......................................................................................................142
Table 47. XOR Chain CMOS....................................................................................................144
Table 48. XOR Chain RAC .......................................................................................................144
Table 49. System Bandwidths ..................................................................................................146
Table 50. Intel 830MP Chipset Ballout Signal Name List.........................................................150
298338-001
Datasheet
9