82830MP Datasheet, PDF (118/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
AGP Transaction Ordering
The GMCH-M observes transaction ordering rules as defined by the AGP 2.0 specification.
AGP Electricals
4x/2x/1x and PCI data transfers use 1.5V signaling levels as described in the AGP 2.0 specification.
Support for PCI-66 Devices
The GMCH-M’s AGP interface may be used as a PCI-66 MHz interface with the following restrictions:
• Support for 1.5-V operation only.
• Support for only one device. GMCH-M will not provide arbitration or electrical support for more
than one PCI-66 device.
• The PCI-66 device must meet the AGP 2.0 electrical specification.
• The GMCH-M does not provide full PCI-to-PCI bridge support between AGP/PCI and hub
interface. Traffic between AGP and hub interface is limited to hub interface-to-AGP memory
writes.
• LOCK# signal is not present. Neither inbound nor outbound locks are supported.
• SERR#/PERR# signals are not present.
• 16-clock Subsequent Data Latency timer (instead of 8)
4x AGP Protocol
In addition to the 1x and 2x AGP protocol the GMCH-M supports 4x AGP read and write data transfers,
and 4x sideband address generation. 4x operation will be compliant with the 4x AGP spec as currently
described in AGP 2.0.
The 4x data transfer protocol provides 1.06 GB/s transfer rates. The control signal protocol for the 4x
data transfer protocol is identical to 1x/2x protocol. In 4x mode 16 bytes of data are transferred during
each 66-MHz clock period. The minimum throttle-able block size remains four 66-MHz clocks which
means 64 bytes of data is transferred per block. Three additional signal pins are required to implement
the 4x data transfer protocol. These signal pins are complementary data transfer strobes for the AD bus
(2) and the SBA bus (1).
Fast Writes
The Fast Write (FW) transaction is from the core logic to the AGP master acting as a PCI target. This
type of access is required to pass data/control directly to the AGP master instead of placing the data into
main memory and then having the AGP master read the data. For 1x transactions, the protocol simply
follows the PCI bus specification. However, for higher speed transactions (2x or 4x), FW transactions
will follow a combination for PCI and AGP bus protocols for data movement.
118
Datasheet
298338-001