82830MP Datasheet, PDF (66/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
4.5.1.22
DRC - DRAM Controller Mode Register - Device #0
Address Offset:
Default Value:
Access:
Size:
7C-7Fh
00000000h
Read/Write
32 bits
Bit
31:30
29
28
27
26:24
23:20
19:15
14
13:11
Description
Specification Revision Number. Hardwired to “00” on GMCH-M.
Initialization Complete (IC): Setting this bit to a “1” enables SDRAM refreshes. On power up and S3 exit,
the BIOS initializes the SDRAM array and sets this bit to a “1”. This bit works in combination with the RMS
bits in controlling refresh state:
IC RMS Refresh State
0 XXX OFF
X 000 OFF
1 001 ON
1 010 ON
1 011 ON
1 111 ON
Default Value=0.
DRAM Row Power- Mgmt Enable: When this bit is set to a 1, a SDRAM row is powered down (issued a
power down command and CKE de-asserted) after the SDRAM idle timer (as programmed in DRT) expires.
During a refresh, rows in the low power state are powered up and refreshed. Hence, coming out of a refresh
all rows will be powered up.
Default Value=0.
Reserved.
Active Row Count: This field determines the number of rows the SDRAM controller allows in the active state
if SDRAM row power management is enabled (bit 28). All populated rows not in the active state are in power
down. An access to a row in power down will cause that row to exit power down, following that the LRU row
is placed into power down if the number of active rows is greater than that allowed by this register.
Bit[26:24] Maximum number of Active Rows
000
All rows allowed to be in active state.
001
1 Row
010
2 Rows
011
3 Rows
100
4 Rows
101
Reserved
110
Reserved
111
Reserved
Default Value=000.
Reserved.
Reserved.
Page Close Enable: When this bit is set to a 1, SDRAM row pages are closed after the SDRAM idle timer
(as programmed in DRT) expires.
Default Value=0.
Reserved
66
Datasheet
298338-001