82830MP Datasheet, PDF (77/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
4.5.1.30
AGPCMD - AGP Command Register - Device #0
Address Offset:
Default Value:
Access:
Size:
A8-ABh
00000000h
Read/Write
32 bits
This register provides control of the AGP operational parameters.
Bit
31:10
9
8
7:6
5
4
3
2:0
Description
Reserved.
SBA Enable. When this bit is set to 1, the side band addressing mechanism is enabled.
Default Value=0.
AGP Enable. When this bit is reset to 0, the GMCH-M will ignore all AGP operations, including the sync
cycle.
Any AGP operations received while this bit is set to 1 will be serviced even if this bit is reset to 0.
If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA command being delivered in
1X mode the command will be issued.
When this bit is set to 1 the GMCH-M will respond to AGP operations delivered via PIPE#, or to operations
delivered via SBA if the AGP Side Band Enable bit is also set to 1.
Default Value=0.
Reserved.
4G. The GMCH-M as an AGP target does not support addressing greater than 4 GB. This bit is hardwired
to 0.
Fast Write Enable
When set to “1” GMCH-M AGP master supports Fast Writes.
When set to “0” Fast Writes are disabled.
Default Value=0.
Reserved.
Data Rate: The settings of these bits determine the AGP data transfer rate. One (and only one) bit in this
field must be set to indicate the desired data transfer rate.
001 = 1X (Bit 0)
010 = 2X (Bit 1)
100 = 4x (Bit 2)
The same bit must be set on both master and target. Configuration software will update this field by setting
only one bit that corresponds to the capability of AGP master (after that capability has been verified by
accessing the same functional register within the AGP masters configuration space.) Note that the
selected data transfer mode applies to both AD bus and SBA bus.
Default Value=000.
298338-001
Datasheet
77