82830MP Datasheet, PDF (79/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
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therefore these bits must be programmed to a smaller practical value that will force adequate address
range to be requested via APBASE register from the PCI configuration software.
Bit
Description
7:6 Reserved
5:3 Graphics Aperture Size (APSIZE) (R/W): Each bit in APSIZE[5:3] operates on similarly ordered bits in
APBASE[27:25] of the Aperture Base configuration register. When a particular bit of this field is “0” it forces
the similarly ordered bit in APBASE[27:25] to behave as “hardwired” to 0. When a particular bit of this field is
set to “1” it allows the corresponding bit of the APBASE[27:25] to be read/write accessible. Only the following
combinations are allowed when the Aperture is enabled:
Bits[5:3] Aperture Size
1 1 1 32 MB
1 1 0 64 MB
1 0 0 128 MB
0 0 0 256 MB
Default for APSIZE[5:3]=000b forces default APBASE[27:25] =000b (i.e. all bits respond as “hardwired” to 0).
This provides maximum aperture size of 256 MB. As another example, programming APSIZE[5:3]=111b
enables APBASE[27:25] as read/write programmable.
2:0 Reserved
4.5.1.34
ATTBASE Aperture Translation Table Base Register - Device #0
Address Offset:
Default Value:
Access:
Size:
B8-BBh
00000000h
Read/Write
32 bits
Note:
This register provides the starting address of the Graphics Aperture Translation Table Base located in the
main DRAM. This value is used by the GMCH-M’s Graphics Aperture address translation logic
(including the GTLB logic) to obtain the appropriate address translation entry required during the
translation of the aperture address into a corresponding physical DRAM address. The ATTBASE
register may be dynamically changed.
The address provided via ATTBASE is 4-KB aligned.
Bit
31: 12
11:0
Description
This field contains a pointer to the base of the translation table used to map memory space addresses in
the aperture range to addresses in main memory.
Reserved
4.5.1.35
AMTTAGP Interface Multi-Transaction Timer Register - Device #0
Address Offset:
Default Value:
Access:
Size:
BCh
00h
Read/Write
8 bits
AMTT is an 8-bit register that controls the amount of time that the GMCH-M’s arbiter allows the
AGP/PCI master to perform multiple back-to-back transactions. The GMCH-M’s AMTT mechanism is
298338-001
Datasheet
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