82830MP Datasheet, PDF (92/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
4.5.2.16
SSTS - Secondary PCI-PCI Status Register - Device #1
Address Offset:
Default Value:
Access:
Size:
1E-1Fh
02A0h
Read Only, Read/Write Clear
16 bits
SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary
side (i.e. PCI1/AGP side) of the “virtual” PCI-PCI bridge embedded within GMCH-M.
Bit
Descriptions
15
Detected Parity Error (DPE1). This bit is set to a 1 to indicate GMCH-M’s detection of a parity error in
the address or data phase of PCI1/AGP bus transactions. Software sets DPE1 to 0 by writing a 1 to
this bit. Note that the function of this bit is not affected by the PERRE1 bit.
Also note that PERR# is not implemented in the GMCH-M.
Default Value=0.
14
Received System Error (SSE1). This bit is hardwired to 0 since the GMCH-M does not have an
SERR# signal pin.
Default Value=0.
13
Received Master Abort Status (RMAS1). When the GMCH-M terminates a Host-to-PCI1/AGP with
an unexpected master abort, this bit is set to 1.
Software resets this bit to 0 by writing a 1 to it.
Default Value=0.
12
Received Target Abort Status (RTAS1). When a GMCH-M-initiated transaction on PCI1/AGP is
terminated with a target abort, RTAS1 is set to 1.
Software resets RTAS1 to 0 by writing a 1 to it.
Default Value=0.
11
Signaled Target Abort Status (STAS1). STAS1 is hardwired to a 0, since the GMCH-M does not
generate target abort on PCI1/AGP.
Default Value=0.
10:9 DEVSEL# Timing (DEVT1). This 2-bit field indicates the timing of the DEVSEL# signal when the
GMCH-M responds as a target on PCI1/AGP, and is hard-wired to the value 01b (medium) to indicate
the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle.
Default Value=01.
8
Data Parity Detected (DPD1). Hardwired to 0. GMCH-M does not implement G_PERR# function.
However, data parity errors are still detected and reported using SERR Hub Interface special cycles(if
enabled by SERRE1 and the BCTRL register, bit 0).
Default Value=0.
7
Fast Back-to-Back (FB2B1). This bit is hardwired to 1 since GMCH-M as a target supports fast back-
to-back transactions on PCI1/AGP.
Default Value=1.
6
Reserved.
5
66/60 MHZ Capability: Hardwired to “1”.
4:0 Reserved.
92
Datasheet
298338-001