82830MP Datasheet, PDF (64/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
4.5.1.21
DRT—DRAM Timing Register - Device #0
Address Offset:
Default Value:
Access:
Size:
78-7Bh
00000010h
Read/Write
32 bits
This register controls the timing of the SDRAM Controller.
Bit
31:19
18:16
15:11
10
9:6
5:4
3
Description
Reserved.
DRAM Idle Timer: This field determines the number of clocks the SDRAM controller allows a row in
the idle state (un-accessed) before pre-charging all pages in that row; or powering down that row
based on the settings of bit 28 and bit 14 of DRC.
Bit[18:16] Idle clocks before Action
0 0 0 Infinite (Counter is disabled and no action is taken)
0 0 1 0 (Not Supported on GMCH-M as this setting requires auto precharge)
010 8
0 1 1 16
1 0 0 64
1 0 1 256
1 1 0 512
1 1 1 1024
DRC 28
DRC 14
Action on Counter Expiration.
(Pwr Dwn Enbl) (Page Cls Enbl)
0
0
None (Counter Disabled)
0
1
Pre-Charge All
1
0
Power Down and De-assert CKE, Pages open.
1
1
Pre-charge All, Power Down and De-assert CKE
Default Value=000.
Recommended settings for DRC 28=1, DRC 14=1 and DRT 18:16 =010.
Reserved
Activate to Precharge delay (tRAS). This bit controls the number of CLKs for tRAS.
0 = tRAS = 7 CLKs
1 = tRAS = 5 CLKs.
Default Value=0.
Reserved
CAS# Latency (tCL). This bit controls the number of CLKs between when a read command is
sampled by the SDRAM and when GMCH-M samples read data from the SDRAM.
00 = Reserved
01 = 3
10 = 2
11 = Reserved
Default Value=01.
Reserved
64
Datasheet
298338-001