82830MP Datasheet, PDF (113/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
R
5.2.5
5.2.6
5.3
5.3.1
In-Order Queue Pipelining
All agents on the CPU bus track the number of pipelined bus transaction with an in-order queue (IOQ).
The GMCH –M can support an IOQ depth of 8 and uses BNR# to guarantee that limit is not exceeded.
Write Combining
To allow for high speed write capability for graphics, the USWC (uncacheable, speculative, write-
combining) memory type provides a write-combining buffering mechanism for write operations. A high
percentage of graphics transactions are writes to the memory-mapped graphics region, normally known
as the linear frame buffer. Reads and writes to USWC are non-cached and can have no side effects.
In the case of graphics, current 32-bit drivers (without modifications) would use Partial Write protocol to
update the frame buffer. The highest performance write transaction on the CPU bus is the Line Write. By
combining several back-to-back Partial write transactions (internal to the CPU) into a Line write
transaction on the CPU bus, the performance of frame buffer accesses would be greatly improved. To
this end, the CPU supports the USWC memory. Writes to USWC memory can be buffered and
combined in the processor's write-combining buffers (WCB). , or the WCB is full (32 bytes)The WCB
can be flushed under different situations*. In order to extend this capability to the current drivers, it is
necessary to set up the linear frame buffer address range to be USWC memory type. This can be done
by programming the MTRR registers in the CPU.
If the number of bytes in the WCB is < 32 then a series of <= 8 byte writes are performed upon WCB
flushing. The GMCH-M further optimizes this by providing write combining for CPU-to-hub interface,
and CPU-to-AGP/PCI Write transactions. If the target of CPU writes is hub interface memory, then the
data is combined and sent to the hub interface bus as a single write burst. The same concept applies to
CPU writes to AGP/PCI memory. The USWC writes that target system SDRAM are handled as regular
system SDRAM writes.
Note that the application of USWC memory attribute is not limited only to the frame buffer support and
that the GMCH-M implements write combining for any CPU-to-hub interface or CPU-to-AGP/PCI
posted write.
*Please refer to the following documents on how to implement write combining buffers: Intel Write
Combining Memory Implementation Guidelines (24422) and Intel^® Architecture Software Developer’s
Manual Volume 3 System Programming Guide (245572)
System Memory Interface
SDRAM Interface Overview
The Intel 830MP chipset integrates a main memory SDRAM controller with a 64-bit wide interface.
830MP’s system memory buffers support LVTTL (SDRAM) signaling at 133 MHz.
• Configured for Single Data Rate SDRAM, the Intel 830MP chipset’s memory interface includes
support for:
• Up to 1.0 GB of 133-MHz SDRAM using 512-Mb technology
• PC133 SO-DIMMs
• Maximum of 2 SO-DIMMs, Single-sided and/or Double-sided
• The 830MP chipset only supports 4 bank memory technologies.
298338-001
Datasheet
113