82830MP Datasheet, PDF (115/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
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lower three bits are strapped on the SA[2:0] pins. SCL and SDA are connected directly to the System
Management Bus on the ICH3-M. Thus data is read from the Serial Presence Detect port on the SO-
DIMMs via a series of IO cycles to the south bridge. BIOS essentially needs to determine the size and
type of memory used for each of the rows of memory in order to properly configure the 830MP memory
interface.
5.3.2.1.2 SDRAM Register Programming
This section provides an overview of how the required information for programming the SDRAM
registers is obtained from the Serial Presence Detect ports on the SO-DIMMs. The Serial Presence
Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength, Row Type (on a row by
row basis), SDRAM Timings, Row Sizes, and Row Page Sizes. The following table lists a subset of the
data available through the on board Serial Presence Detect ROM on each SO-DIMM.
Table 29. Data Bytes on SO-DIMM Used for Programming SDRAM Registers
Byte
Function
2
3
4
5
11
12
17
36-41
42
126
Memory Type (EDO, SDR SDRAM)
# of Row Addresses, not counting Bank Addresses
# of Column Addresses
# of banks of SDRAM (Single or Double sided SO-DIMM)
ECC, no ECC
Refresh Rate
# Banks on each Device
Access Time from Clock for CAS# Latency 1 through 7
Data Width of SDRAM Components
Memory Frequency
5.3.3
Table 29 is only a subset of the defined SPD bytes on the SO-DIMMs. These bytes collectively provide
enough data for programming the 830MP SDRAM registers
SDRAM Address Translation and Decoding
The Intel 830MP chipset contains address decoders that translate the address received on the host bus, or
the hub interface to an effective memory address. Decoding and Translation of these addresses vary with
the three SDRAM types. Also, the number of pages, page sizes, and densities supported vary with the 4
SDRAM types. In general, the Intel 830MP chipset supports 64 Mb, 128 Mb, 256 Mb, and 512 Mb
SDRAM devices. The multiplexed row/column address to the SDRAM memory array is provided by the
SM_BA[1:0] and SM_MA[12:0] signals. These addresses are derived from the host address bus as
defined by the table above for SDRAM devices.
298338-001
Datasheet
115