82830MP Datasheet, PDF (117/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
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5.4.1 AGP Target Operations
As an initiator, the GMCH-M does not initiate cycles using AGP enhanced protocols. The GMCH-M
supports AGP target interface to main memory only. The GMCH-M supports interleaved AGP and PCI
transactions.
The following table summarizes target operation support of GMCH-M for AGP masters.
Table 31. AGP Commands Supported by GMCH-M When Acting as an AGP Target
AGP Command
C/BE[3:0]#
GMCH-M Host Bridge
Read
Hi-Priority Read
Reserved
Reserved
Write
Hi-Priority Write
Encoding
0000
0000
0001
0000
0010
0011
0100
0100
0101
0101
Cycle Destination
Main Memory
Hub interface
Main Memory
hub interface
N/A
N/A
Main Memory
hub interface
Main Memory
hub interface
Reserved
Reserved
Long Read
0110
0111
1000
N/A
N/A
Main Memory
Hub interface
Hi-Priority Long Read
1001
Flush
Reserved
Fence
1010
1011
1100
Main Memory
Hub interface
GMCH-M
N/A
GMCH-M
Reserved
1101
N/A
Reserved
1110
N/A
Reserved
1111
N/A
NOTE: N/A refers to a function that is not applicable.
Response as AGP Target
Low Priority Read
Complete with random data
High Priority Read
Complete with random data
No Response
No Response
Low Priority Write
Cycle goes to SDRAM with BE’s inactive
High Priority Write
Cycle goes to SDRAM with BE’s inactive
- does not go to hub interface
No Response
No Response
Low Priority Read
Complete locally with random data -
does not go to hub interface
High Priority Read
Complete with random data
Complete with QW of Random Data
No Response
No Response – Flag inserted in GMCH-
M request queue
No Response
No Response
No Response
As a target of an AGP cycle, the GMCH-M supports all the transactions targeted at main memory and
summarized in the table above. The GMCH-M supports both normal and high priority read and write
requests. The GMCH-M will not support AGP cycles to hub interface. AGP cycles do not require
coherency management and all AGP initiator accesses to main memory using AGP protocol are treated
as non-snoopable cycles. These accesses are directed to the AGP aperture in main memory that is
programmed as either uncacheable (UC) memory or write combining (WC) in the processor’s MTRRs.
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Datasheet
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