82830MP Datasheet, PDF (22/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
3.2
System Memory Interface
Table 3. System Memory Interface Signal Descriptions
Signal Name
Type
Description
SM_MA[12:0]
SM_BA[1:0]
SM_MD[63:0]
SM_DQM[7:0]
SM_CS[3:0]#
SM_RAS#
SM_CAS#
SM_WE#
SM_CKE[3:0]
SM_OCLK
SM_RCLK
SM_CLK [3:0]
SM_RCOMP
O
LVTTL
O
LVTTL
I/O
LVTTL
O
LVTTL
OLVTTL
O
LVTTL
O
LVTTL
O
LVTTL
O
LVTTL
O
LVTTL
I
LVTTL
O
LVTTL
I/O
Memory Address: SM_MA[12:0] are used to provide the multiplexed row and
column address to SDRAM.
Memory Bank Address: These signals define the banks that are selected
within each SDRAM row. The SM_MAn and SM_BA signals combine to
address every possible location within a SDRAM device.
Memory Data: These signals are used to interface to the SDRAM data bus.
Input/Output Data Mask: These pins act as synchronized output enables
during read cycles and as byte enables during write cycles.
Chip Select: For the memory rows configured with SDRAM, these pins
perform the function of selecting the particular SDRAM components during the
active state. Note: There is one SM_CS per SDRAM row. These signals can
be toggled on every rising System Memory Clock edge.
SDRAM Row Address Strobe: A table of the SDRAM commands supported
by 830MP is given in the SDRAM section. SM_RAS# may be heavily loaded
and requires 2 SDRAM clock cycles for setup time to the SDRAMs.
SDRAM Column Address Strobe: A table of the SDRAM commands
supported by 830MP is given in the SDRAM section. SM_CAS# may be
heavily loaded and requires 2 SDRAM clock cycles for setup time to the
SDRAMs.
Write Enable Signal: SM_WE# is asserted during writes to SDRAM. Refer
to truth table of the SDRAM commands supported by 830MP, given in the
SDRAM section. SM_WE# may be heavily loaded and requires 2 SDRAM
clock cycles for setup time to the SDRAMs.
Clock Enable: These signals are used to signal a self refresh or power down
command to a SDRAM array when entering system suspend. SM_CKE is
also used to dynamically power down inactive SDRAM rows. There is one
SM_CKE per SDRAM row. These signals can be toggled on every rising
SM_CLK Clock edge.
System Memory Output Clock: This signal delivers a synchronized clock to
the SM_RCLK pin.
System Memory Return Clock: This signal receives the synchronized clock
from SM_OCLK.
System Memory Clock: These signals deliver a synchronized clock to the
SDRAMs.
System Memory RCOMP: Used to calibrate the system memory I/O buffers.
This pin should be connected to a 27.5-Ω resistor tied to Vss.
Total pins for System Memory Section: 105.
22
Datasheet
298338-001