82830MP Datasheet, PDF (96/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
R
4.5.2.21
Note that prefetchable memory range is supported to allow segregation by the configuration software
between the memory ranges that must be defined as UC and the ones that can be designated as a USWC
(i.e. prefetchable) from the CPU perspective.
BCTRL - PCI-PCI Bridge Control Register - Device #1
Address Offset:
Default Value:
Access:
Size
3Eh
00h
Read/Write
8 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The
BCTRL provides additional control for the secondary Interface (i.e. PCI1/AGP) as well as some bits that
affect the overall behavior of the “virtual” PCI-PCI bridge embedded within GMCH-M, e.g. VGA
compatible address ranges mapping.
Bit
Descriptions
7
Fast Back-to-Back Enable: Since there is only one target allowed on AGP this bit is meaningless. This
bit is hardwired to 0.
6
Secondary Bus Reset: GMCH-M does not support generation of reset via this bit on the AGP and
therefore this bit is hardwired to 0.
Note that the only way to perform a hard reset of the AGP is via the system reset either initiated by
software or hardware via ICH3-M.
5
Master Abort Mode: This bit is hardwired to 0. This means when acting as a master on AGP/PCI1 the
GMCH-M will drop writes on the “floor” and return all 1 during reads when a Master Abort occurs.
Default Value=0.
4
Reserved.
96
Datasheet
298338-001