82830MP Datasheet, PDF (120/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel® 830MP Chipset
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5.4.8.2 GMCH-M Initiator and Target Operations
The following table summarizes target operation support of GMCH-M for AGP/PCI1 bus initiators. The
cycles can be either destined to main memory or the hub interface bus.
Table 32. PCI Commands Supported by GMCH-M When Acting as a PCI Target
PCI Command
C/BE[3:0]# Encoding
GMCH-M
Interrupt Acknowledge
0000
Special Cycle
0001
I/O Read
0010
I/O Write
0011
Reserved
0100
Reserved
0101
Memory Read
0110
0110
Memory Write
0111
0111
Reserved
1000
Reserved
1001
Configuration Read
1010
Configuration Write
1011
Memory Read Multiple
1100
1100
Dual Address Cycle
1101
Memory Read Line
1110
1110
Memory Write and Invalidate
1111
1111
NOTE: N/A refers to a function that is not applicable.
Cycle Destination
N/A
N/A
N/A
N/A
N/A
N/A
Main Memory
hub interface
Main Memory
hub interface
N/A
N/A
N/A
N/A
Main Memory
hub interface
N/A
Main Memory
hub interface
Main Memory
hub interface
Response as PCI Target
No Response
No Response
No Response
No Response
No Response
No Response
Read
No Response
Posts Data
No Response
No Response
No Response
No Response
No Response
Read
No Response
No Response
Read
No Response
Posts Data
No Response
As a target of an AGP/PCI cycle, GMCH-M only supports the following transactions:
Memory Read - The GMCH-M will issue one snoop and the entire cache line of read data will be
buffered. If a Memory Read bursts across the cache line another snoop will be issued but the
transaction will be disconnected on the cache line boundary. Subsequent Memory Read
transaction hitting the cache line buffer will return data from the buffer.
Memory Read Line, and Memory Read Multiple - These commands are supported identically by the
GMCH-M. The GMCH-M issues two snoops (a snoop followed by a snoop-ahead) on the
host bus and releases the CPU bus for other traffic. When the first DW of the first cache line
is delivered and FRAME# is still asserted, the GMCH-M will issue another snoop-ahead on
the host bus. This allows the GMCH-M to continuously supply data during Memory Read
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Datasheet
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