82830MP Datasheet, PDF (129/159 Pages) Intel Corporation – Intel 830MP Chipset: 82830MP Graphics and Memory Controller Hub (GMCH-M)

Intel^® 830MP Chipset
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4. XOR chain patterns can be applied to all GMCH-M interfaces (except for RAC) after PCIRST# is
deasserted.
5. DVOA_D[11;8:6;4:3] and G_PAR/ADD_DETECT can be “Don’t care”. See Figure 11 for more
details.
Figure 11. XOR Chain Test Mode Entry Events Diagram
PCIRST#
DVOA_D[3]
DVOA_D[4]
DVOA_D[6]
DVOA_D[7]
DVOA_D[8]
DVOA_D[11]
G_PAR
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
5.7.1.2
The assertion of DVOA_D[6] high in Figure 11 is optional. The 830MP chipset supports dual ended
termination for the CPU but only single ended termination is necessary when using the XOR test chains.
RAC Chain Initialization
On the RAC chain, special timing requirements need to be followed in order to use it. The event
sequence (see Section 5.7.1.2) to enter test mode for the RAC chain is identical to that for all other
chains and is shown in Figure 11 above. The application of test patterns to the inputs of the RAC chain
must adhere to the timing requirements shown in Figure 12. Table 35 lists the minimum and maximum
timings for the time parameters in Figure 12. This includes the maximum test enable (t1) and output
propagation delays (t2), and minimum period for the application of a test pattern (t3).
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Datasheet
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